URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 120 and 122

Rev 120	Rev 122
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.23 2003/04/10 12:43:19 simont`
	`// defines for pherypherals added`
	`//`
`// Revision 1.22 2003/04/09 16:24:04 simont`	`// Revision 1.22 2003/04/09 16:24:04 simont`
`// change wr_sft to 2 bit wire.`	`// change wr_sft to 2 bit wire.`
`//`	`//`
`// Revision 1.21 2003/04/09 15:49:42 simont`	`// Revision 1.21 2003/04/09 15:49:42 simont`
`// Register oc8051_sfr dato output, add signal wait_data.`	`// Register oc8051_sfr dato output, add signal wait_data.`
Line 410...	Line 413...
`.des(des1_r));`	`.des(des1_r));`


`//`	`//`
`//program rom`	`//program rom`
	`ifdef OC8051_ROM
`oc8051_rom oc8051_rom1(.rst(wb_rst_i),`	`oc8051_rom oc8051_rom1(.rst(wb_rst_i),`
`.clk(wb_clk_i),`	`.clk(wb_clk_i),`
`.ea_int(ea_int),`	`.ea_int(ea_int),`
`.addr(iadr_o),`	`.addr(iadr_o),`
`.data1(op1_i),`	`.data1(op1_i),`
`.data2(op2_i),`	`.data2(op2_i),`
`.data3(op3_i));`	`.data3(op3_i));`
	`else
	`assign ea_int = 1'b0;`
	`assign op1_i = 8'h00;`
	`assign op2_i = 8'h00;`
	`assign op3_i = 8'h00;`
	`endif

`//`	`//`
`//`	`//`
`oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),`	`oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),`
`.cy_in(cy),`	`.cy_in(cy),`