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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 132 and 134
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| Rev 132 |
Rev 134 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.25 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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//
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// Revision 1.24 2003/04/11 10:05:59 simont
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// Revision 1.24 2003/04/11 10:05:59 simont
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// deifne OC8051_ROM added
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// deifne OC8051_ROM added
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//
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//
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// Revision 1.23 2003/04/10 12:43:19 simont
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// Revision 1.23 2003/04/10 12:43:19 simont
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// defines for pherypherals added
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// defines for pherypherals added
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| Line 410... |
Line 413... |
.eq(eq),
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.eq(eq),
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.b_in(bit_out),
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.b_in(bit_out),
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.cy(cy),
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.cy(cy),
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.acc(acc),
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.acc(acc),
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.des(des1)
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.des(des1)
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// .comp_wait(comp_wait)
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);
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);
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//
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//
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//program rom
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//program rom
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| Line 498... |
Line 500... |
.dack_i(wbd_ack_i),
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.dack_i(wbd_ack_i),
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// from decoder
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// from decoder
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.rd_sel(ram_rd_sel),
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.rd_sel(ram_rd_sel),
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.wr_sel(ram_wr_sel),
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.wr_sel(ram_wr_sel),
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.rn({bank_sel, op1_n[2:0]}),
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.rn({bank_sel, op1_cur}),
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.rd_ind(rd_ind),
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.rd_ind(rd_ind),
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.rd(rd),
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.rd(rd),
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.mem_act(mem_act),
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.mem_act(mem_act),
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.mem_wait(mem_wait),
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.mem_wait(mem_wait),
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