URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 134 and 139

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 134	Rev 139
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.26 2003/04/29 11:24:31 simont`
	`// fix bug in case execution of two data dependent instructions.`
	`//`
`// Revision 1.25 2003/04/25 17:15:51 simont`	`// Revision 1.25 2003/04/25 17:15:51 simont`
`// change branch instruction execution (reduse needed clock periods).`	`// change branch instruction execution (reduse needed clock periods).`
`//`	`//`
`// Revision 1.24 2003/04/11 10:05:59 simont`	`// Revision 1.24 2003/04/11 10:05:59 simont`
`// deifne OC8051_ROM added`	`// deifne OC8051_ROM added`
Line 228...	Line 231...
`op2_i,`	`op2_i,`
`op3_i,`	`op3_i,`
`dptr_hi,`	`dptr_hi,`
`dptr_lo,`	`dptr_lo,`
`ri,`	`ri,`
`rn_mem,`
`data_out,`	`data_out,`
`op1,`	`op1,`
`op2,`	`op2,`
`op3,`	`op3,`
`acc,`	`acc,`
Line 280...	Line 282...
`wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)`	`wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)`

`wire [7:0] src1, //alu sources 1`	`wire [7:0] src1, //alu sources 1`
`src2, //alu sources 2`	`src2, //alu sources 2`
`src3, //alu sources 3`	`src3, //alu sources 3`
	`des_acc,`
`des1, //alu destination 1`	`des1, //alu destination 1`
`des2; //alu destinations 2`	`des2; //alu destinations 2`
`wire desCy, //carry out`	`wire desCy, //carry out`
`desAc,`	`desAc,`
`desOv, //overflow`	`desOv, //overflow`
Line 362...	Line 365...
`.src1(src1),`	`.src1(src1),`
`.src2(src2),`	`.src2(src2),`
`.src3(src3),`	`.src3(src3),`
`.srcCy(alu_cy),`	`.srcCy(alu_cy),`
`.srcAc(srcAc),`	`.srcAc(srcAc),`
	`.des_acc(des_acc),`
`.des1(des1),`	`.des1(des1),`
`.des2(des2),`	`.des2(des2),`
`.desCy(desCy),`	`.desCy(desCy),`
`.desAc(desAc),`	`.desAc(desAc),`
`.desOv(desOv),`	`.desOv(desOv),`
Line 412...	Line 416...
`oc8051_comp oc8051_comp1(.sel(comp_sel),`	`oc8051_comp oc8051_comp1(.sel(comp_sel),`
`.eq(eq),`	`.eq(eq),`
`.b_in(bit_out),`	`.b_in(bit_out),`
`.cy(cy),`	`.cy(cy),`
`.acc(acc),`	`.acc(acc),`
`.des(des1)`	`.des(des_acc)`
`);`	`);`


`//`	`//`
`//program rom`	`//program rom`
Line 443...	Line 447...
`.data_out(alu_cy));`	`.data_out(alu_cy));`
`//`	`//`
`//`	`//`
`oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),`	`oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),`
`.rst(wb_rst_i),`	`.rst(wb_rst_i),`
`.rd_addr(rd_addr),`
`.wr_addr(wr_addr),`	`.wr_addr(wr_addr),`
`.data_in(wr_dat),`	`.data_in(wr_dat),`
`.wr(wr_o),`	`.wr(wr_o),`
`.wr_bit(bit_addr_o),`	`.wr_bit(bit_addr_o),`
`.rn_out(rn_mem),`
`.ri_out(ri),`	`.ri_out(ri),`
`.sel(op1_cur),`	`.sel(op1_cur[0]),`
`.bank(bank_sel));`	`.bank(bank_sel));`



`assign icyc_o = istb_o;`	`assign icyc_o = istb_o;`
Line 466...	Line 468...
`.wr_i(wr),`	`.wr_i(wr),`
`.wr_o(wr_o),`	`.wr_o(wr_o),`
`.wr_bit_i(bit_addr),`	`.wr_bit_i(bit_addr),`
`.wr_bit_o(bit_addr_o),`	`.wr_bit_o(bit_addr_o),`
`.wr_dat(wr_dat),`	`.wr_dat(wr_dat),`
	`.des_acc(des_acc),`
`.des1(des1),`	`.des1(des1),`
`.des2(des2),`	`.des2(des2),`
`.rd_addr(rd_addr),`	`.rd_addr(rd_addr),`
`.wr_addr(wr_addr),`	`.wr_addr(wr_addr),`
`.wr_ind(wr_ind),`	`.wr_ind(wr_ind),`
Line 531...	Line 534...

`// sfr's`	`// sfr's`
`.sp_w(sp_w),`	`.sp_w(sp_w),`
`.dptr({dptr_hi, dptr_lo}),`	`.dptr({dptr_hi, dptr_lo}),`
`.ri(ri),`	`.ri(ri),`
`.rn_mem(rn_mem),`
`.acc(acc),`	`.acc(acc),`
`.sp(sp)`	`.sp(sp)`
`);`	`);`


Line 547...	Line 549...
`.adr0(rd_addr[7:0]),`	`.adr0(rd_addr[7:0]),`
`.adr1(wr_addr[7:0]),`	`.adr1(wr_addr[7:0]),`
`.dat0(sfr_out),`	`.dat0(sfr_out),`
`.dat1(wr_dat),`	`.dat1(wr_dat),`
`.dat2(des2),`	`.dat2(des2),`
	`.des_acc(des_acc),`
`.we(wr_o && !wr_ind),`	`.we(wr_o && !wr_ind),`
`.bit_in(desCy),`	`.bit_in(desCy),`
`.bit_out(sfr_bit),`	`.bit_out(sfr_bit),`
`.wr_bit(bit_addr_o),`	`.wr_bit(bit_addr_o),`
`.ram_rd_sel(ram_rd_sel),`	`.ram_rd_sel(ram_rd_sel),`

Browse

Tools

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 134 and 139