URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 139 and 141

Rev 139	Rev 141
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.27 2003/05/05 15:46:37 simont`
	`// add aditional alu destination to solve critical path.`
	`//`
`// Revision 1.26 2003/04/29 11:24:31 simont`	`// Revision 1.26 2003/04/29 11:24:31 simont`
`// fix bug in case execution of two data dependent instructions.`	`// fix bug in case execution of two data dependent instructions.`
`//`	`//`
`// Revision 1.25 2003/04/25 17:15:51 simont`	`// Revision 1.25 2003/04/25 17:15:51 simont`
`// change branch instruction execution (reduse needed clock periods).`	`// change branch instruction execution (reduse needed clock periods).`
Line 248...	Line 251...
`wire [15:0] pc;`	`wire [15:0] pc;`

`assign wbd_cyc_o = wbd_stb_o;`	`assign wbd_cyc_o = wbd_stb_o;`

`wire src_sel3;`	`wire src_sel3;`
`wire [1:0] wr_sfr;`	`wire [1:0] wr_sfr,`
	`src_sel2;`
`wire [2:0] ram_rd_sel, // ram read`	`wire [2:0] ram_rd_sel, // ram read`
`ram_wr_sel, // ram write`	`ram_wr_sel, // ram write`
`src_sel2,`
`src_sel1;`	`src_sel1;`

`wire [7:0] ram_data,`	`wire [7:0] ram_data,`
`ram_out, //data from ram`	`ram_out, //data from ram`
`sfr_out,`	`sfr_out,`