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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 144 and 148

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Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.29  2003/05/07 12:36:03  simont
 
// chsnge comp.des to des1
 
//
// Revision 1.28  2003/05/06 09:41:35  simont
// Revision 1.28  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
//
// Revision 1.27  2003/05/05 15:46:37  simont
// Revision 1.27  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
// add aditional alu destination to solve critical path.
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// synopsys translate_off
// synopsys translate_off
`include "oc8051_timescale.v"
`include "oc8051_timescale.v"
// synopsys translate_on
// synopsys translate_on
 
 
 
`include "oc8051_defines.v"
 
 
module oc8051_top (wb_rst_i, wb_clk_i,
module oc8051_top (wb_rst_i, wb_clk_i,
//interface to instruction rom
//interface to instruction rom
                wbi_adr_o,
                wbi_adr_o,
                wbi_dat_i,
                wbi_dat_i,
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// interrupt interface
// interrupt interface
                int0_i,
                int0_i,
                int1_i,
                int1_i,
 
 
// external access (active low)
 
                ea_in,
 
 
 
// port interface
// port interface
  `ifdef OC8051_PORTS
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
        `ifdef OC8051_PORT0
                p0_i,
                p0_i,
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        `ifdef OC8051_TC01
        `ifdef OC8051_TC01
                t0_i, t1_i,
                t0_i, t1_i,
        `endif
        `endif
 
 
        `ifdef OC8051_TC2
        `ifdef OC8051_TC2
                t2_i, t2ex_i
                t2_i, t2ex_i,
        `endif
        `endif
 
 
 
// external access (active low)
 
                ea_in
                );
                );
 
 
 
 
 
 
input         wb_rst_i,         // reset input
input         wb_rst_i,         // reset input
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`ifdef OC8051_TC2
`ifdef OC8051_TC2
input         t2_i,             // counter 2 input
input         t2_i,             // counter 2 input
              t2ex_i;           //
              t2ex_i;           //
`endif
`endif
 
 
wire [7:0]  op1_i,
wire [7:0]  dptr_hi,
            op2_i,
 
            op3_i,
 
            dptr_hi,
 
            dptr_lo,
            dptr_lo,
            ri,
            ri,
            data_out,
            data_out,
            op1,
            op1,
            op2,
            op2,
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            p2_out,
            p2_out,
            p3_out,
            p3_out,
            sp,
            sp,
            sp_w;
            sp_w;
 
 
 
wire [31:0] idat_onchip;
 
 
wire [15:0] pc;
wire [15:0] pc;
 
 
assign wbd_cyc_o = wbd_stb_o;
assign wbd_cyc_o = wbd_stb_o;
 
 
wire        src_sel3;
wire        src_sel3;
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                               .mem_act(mem_act),
                               .mem_act(mem_act),
                               .mem_wait(mem_wait),
                               .mem_wait(mem_wait),
                               .wait_data(wait_data));
                               .wait_data(wait_data));
 
 
 
 
 
wire [7:0] sub_result;
//
//
//alu
//alu
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .clk(wb_clk_i),
                       .op_code(alu_op),
                       .op_code(alu_op),
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                       .src2(src2),
                       .src2(src2),
                       .src3(src3),
                       .src3(src3),
                       .srcCy(alu_cy),
                       .srcCy(alu_cy),
                       .srcAc(srcAc),
                       .srcAc(srcAc),
                       .des_acc(des_acc),
                       .des_acc(des_acc),
 
                       .sub_result(sub_result),
                       .des1(des1),
                       .des1(des1),
                       .des2(des2),
                       .des2(des2),
                       .desCy(desCy),
                       .desCy(desCy),
                       .desAc(desAc),
                       .desAc(desAc),
                       .desOv(desOv),
                       .desOv(desOv),
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oc8051_comp oc8051_comp1(.sel(comp_sel),
oc8051_comp oc8051_comp1(.sel(comp_sel),
                         .eq(eq),
                         .eq(eq),
                         .b_in(bit_out),
                         .b_in(bit_out),
                         .cy(cy),
                         .cy(cy),
                         .acc(acc),
                         .acc(acc),
                         .des(des1)
                         .des(sub_result)
                         );
                         );
 
 
 
 
//
//
//program rom
//program rom
`ifdef OC8051_ROM
`ifdef OC8051_ROM
  oc8051_rom oc8051_rom1(.rst(wb_rst_i),
  oc8051_rom oc8051_rom1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .clk(wb_clk_i),
                       .ea_int(ea_int),
                       .ea_int(ea_int),
                       .addr(iadr_o),
                       .addr(iadr_o),
                       .data1(op1_i),
                       .data_o(idat_onchip)
                       .data2(op2_i),
                       );
                       .data3(op3_i));
 
`else
`else
  assign ea_int = 1'b0;
  assign ea_int = 1'b0;
  assign op1_i = 8'h00;
  assign idat_onchip = 32'h0;
  assign op2_i = 8'h00;
 
  assign op3_i = 8'h00;
 
`endif
`endif
 
 
//
//
//
//
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
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                       .iadr_o(iadr_o),
                       .iadr_o(iadr_o),
                       .idat_i(idat_i),
                       .idat_i(idat_i),
                       .istb_o(istb_o),
                       .istb_o(istb_o),
 
 
// internal instruction rom
// internal instruction rom
                       .op1_i(op1_i),
                       .idat_onchip(idat_onchip),
                       .op2_i(op2_i),
 
                       .op3_i(op3_i),
 
 
 
// data memory
// data memory
                       .dadr_o(wbd_adr_o),
                       .dadr_o(wbd_adr_o),
                       .ddat_o(wbd_dat_o),
                       .ddat_o(wbd_dat_o),
                       .dwe_o(wbd_we_o),
                       .dwe_o(wbd_we_o),
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        .stb_o(wbi_stb_o),
        .stb_o(wbi_stb_o),
        .adr_o(wbi_adr_o),
        .adr_o(wbi_adr_o),
        .ack_i(wbi_ack_i),
        .ack_i(wbi_ack_i),
        .cyc_o(wbi_cyc_o));
        .cyc_o(wbi_cyc_o));
 
 
defparam oc8051_icache1.ADR_WIDTH = 7;  // cache address wihth
  defparam oc8051_icache1.ADR_WIDTH = 6;  // cache address wihth
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
defparam oc8051_icache1.BL_NUM = 31; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
  defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
defparam oc8051_icache1.CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
  defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
 
 
//
//
//    no cache
//    no cache
//
//
`else
`else
 
 
 
  `ifdef OC8051_WB
 
 
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
// cpu
// cpu
        .adr_i(iadr_o),
        .adr_i(iadr_o),
        .dat_o(idat_i),
        .dat_o(idat_i),
        .stb_i(istb_o),
        .stb_i(istb_o),
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        .stb_o(wbi_stb_o),
        .stb_o(wbi_stb_o),
        .adr_o(wbi_adr_o),
        .adr_o(wbi_adr_o),
        .ack_i(wbi_ack_i),
        .ack_i(wbi_ack_i),
        .cyc_o(wbi_cyc_o));
        .cyc_o(wbi_cyc_o));
 
 
 
  `else
 
 
 
    assign wbi_adr_o = iadr_o    ;
 
    assign idat_i    = wbi_dat_i ;
 
    assign wbi_stb_o = 1'b1      ;
 
    assign iack_i    = wbi_ack_i ;
 
    assign wbi_cyc_o = 1'b1      ;
 
 
 
  `endif
 
 
`endif
`endif
 
 
 
 
 
 

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