URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 174 and 181

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Rev 174	Rev 181
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.32 2003/06/20 13:36:37 simont`
	`// ram modules added.`
	`//`
`// Revision 1.31 2003/06/17 14:17:22 simont`	`// Revision 1.31 2003/06/17 14:17:22 simont`
`// BIST signals added.`	`// BIST signals added.`
`//`	`//`
`// Revision 1.30 2003/06/03 16:51:24 simont`	`// Revision 1.30 2003/06/03 16:51:24 simont`
`// include "8051_defines" added.`	`// include "8051_defines" added.`
Line 476...	Line 479...
`.data_o(idat_onchip)`	`.data_o(idat_onchip)`
`);`	`);`
`else	`else
`assign ea_int = 1'b0;`	`assign ea_int = 1'b0;`
`assign idat_onchip = 32'h0;`	`assign idat_onchip = 32'h0;`

	`ifdef OC8051_SIMULATION

	`initial`
	`begin`
	`$display("\t * ");`
	`$display("\t * Internal rom disabled!!!");`
	`$display("\t * ");`
	`end`

	`endif

`endif	`endif

`//`	`//`
`//`	`//`
`oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),`	`oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),`
Line 703...	Line 718...
`defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)`	`defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)`



`ifdef OC8051_SIMULATION	`ifdef OC8051_SIMULATION
`initial`
`$display(" Instruction cache enabled");`

	`initial`
	`begin`
	`#1`
	`$display("\t * ");`
	`$display("\t * External rom interface: cache");`
	`$display("\t * ");`
	`end`

`endif	`endif



`//`	`//`
`// no cache`	`// no cache`
`//`	`//`
`else	`else

Line 736...	Line 757...
`.adr_o(wbi_adr_o),`	`.adr_o(wbi_adr_o),`
`.ack_i(wbi_ack_i),`	`.ack_i(wbi_ack_i),`
`.cyc_o(wbi_cyc_o));`	`.cyc_o(wbi_cyc_o));`

`ifdef OC8051_SIMULATION	`ifdef OC8051_SIMULATION
`initial`
`$display(" Wishbone instruction interface enabled");`

	`initial`
	`begin`
	`#1`
	`$display("\t * ");`
	`$display("\t * External rom interface: WB interface");`
	`$display("\t * ");`
	`end`

`endif	`endif

`else	`else

Line 751...	Line 777...
`assign wbi_stb_o = 1'b1 ;`	`assign wbi_stb_o = 1'b1 ;`
`assign iack_i = wbi_ack_i ;`	`assign iack_i = wbi_ack_i ;`
`assign wbi_cyc_o = 1'b1 ;`	`assign wbi_cyc_o = 1'b1 ;`

`ifdef OC8051_SIMULATION	`ifdef OC8051_SIMULATION

`initial`	`initial`
`$display(" Pipelined instruction interface enabled");`	`begin`
	`#1`
	`$display("\t * ");`
	`$display("\t * External rom interface: Pipelined interface");`
	`$display("\t * ");`
	`end`

`endif	`endif


`endif	`endif

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 174 and 181