| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2002/10/23 16:53:39 simont
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// fix bugs in instruction interface
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//
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// Revision 1.14 2002/10/17 18:50:00 simont
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// Revision 1.14 2002/10/17 18:50:00 simont
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// cahnge interface to instruction rom
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// cahnge interface to instruction rom
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//
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//
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// Revision 1.13 2002/09/30 17:33:59 simont
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// Revision 1.13 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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| Line 349... |
Line 352... |
.pc(pc), .out_addr(iadr_o));
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.pc(pc), .out_addr(iadr_o));
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//
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//
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//
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//
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oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
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oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
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.dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o), .wr(wr_xaddr));
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.dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o),
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.wr(wr_xaddr), .stb(stb_o));
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//
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//
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//
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//
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oc8051_ram_sel oc8051_ram_sel1(.addr(rd_addr_r), .bit_in(bit_data), .in_ram(ram_data),
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oc8051_ram_sel oc8051_ram_sel1(.addr(rd_addr_r), .bit_in(bit_data), .in_ram(ram_data),
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.psw(psw_r), .acc(acc), .dptr_hi(dptr_hi), .ports_in(ports_in), .sp(sp_r),
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.psw(psw_r), .acc(acc), .dptr_hi(dptr_hi), .ports_in(ports_in), .sp(sp_r),
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