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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 8 and 9
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Rev 8 |
Rev 9 |
Line 165... |
Line 165... |
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//
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//
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// comp_sel select source1 and source2 to compare
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// comp_sel select source1 and source2 to compare
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// eq result (from comp1 to decoder)
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// eq result (from comp1 to decoder)
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// wad2, wad2_r write to accumulator from destination 2
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// wad2, wad2_r write to accumulator from destination 2
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wire [2:0] comp_sel;
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wire [1:0] comp_sel;
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wire eq, wad2, wad2_r;
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wire eq, wad2, wad2_r;
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//
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//
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// bit_addr bit addresable instruction
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// bit_addr bit addresable instruction
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