URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Diff between revs 5 and 8

Rev 5	Rev 8
Line 1...	Line 1...
	`// synopsys translate_off`
	`include "oc8051_timescale.v"
	`// synopsys translate_on`

	`include "oc8051_defines.v"

`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`	`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`
`rxd, txd, intr, t1_ow);`	`rxd, txd, intr, t1_ow);`

`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`	`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`
`input [7:0] rd_addr, data_in, wr_addr;`	`input [7:0] rd_addr, data_in, wr_addr;`