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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Diff between revs 110 and 127
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Rev 127 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/04/03 19:19:02 simont
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// change adr_i and adr_o length.
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//
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// Revision 1.2 2003/01/13 14:14:41 simont
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// Revision 1.2 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.1 2002/10/28 16:42:08 simont
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// Revision 1.1 2002/10/28 16:42:08 simont
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// initial import
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// initial import
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Line 96... |
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//
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//
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// internal bufers and wires
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// internal bufers and wires
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//
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//
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reg [15:0] adr;
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reg [15:0] adr;
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reg stb;
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//reg stb;
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assign ack_o = ack_i;
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assign ack_o = ack_i;
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assign dat_o = dat_i;
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assign dat_o = dat_i;
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assign stb_o = stb || ack_i;
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assign stb_o = stb_i || ack_i;
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assign cyc_o = stb;
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assign cyc_o = stb_i || ack_i;
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assign adr_o = ack_i ? adr : adr_i;
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assign adr_o = ack_i ? adr : adr_i;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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stb <= #1 1'b0;
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// stb <= #1 1'b0;
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adr <= #1 16'h0000;
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adr <= #1 16'h0000;
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end else begin
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end else begin
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stb <= #1 stb_i;
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// stb <= #1 stb_i;
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adr <= #1 adr_i;
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adr <= #1 adr_i;
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end
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end
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endmodule
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endmodule
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No newline at end of file
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