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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Diff between revs 136 and 138
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| Rev 136 |
Rev 138 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/05/05 10:34:27 simont
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// registering outputs.
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//
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// Revision 1.4 2003/04/16 10:02:45 simont
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// Revision 1.4 2003/04/16 10:02:45 simont
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// fix bug (cyc_o and stb_o)
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// fix bug (cyc_o and stb_o)
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//
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//
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// Revision 1.3 2003/04/03 19:19:02 simont
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// Revision 1.3 2003/04/03 19:19:02 simont
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// change adr_i and adr_o length.
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// change adr_i and adr_o length.
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| Line 116... |
Line 119... |
always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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adr_o <= #1 16'h0000;
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adr_o <= #1 16'h0000;
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end else if (ack_i) begin
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end else if (ack_i) begin
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stb_o <= #1 1'b0;
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stb_o <= #1 stb_i;
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adr_o <= #1 adr_i;
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end else if (!stb_o & stb_i) begin
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end else if (!stb_o & stb_i) begin
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stb_o <= #1 1'b1;
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stb_o <= #1 1'b1;
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adr_o <= #1 adr_i;
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adr_o <= #1 adr_i;
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end
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end
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