| Line 38... |
Line 38... |
----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1.1.1 2003/10/20 03:51:08 srmcqueen
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-- First Upload, working module
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--
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--
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--
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-- This module implements the DES 56-bit Key Block Cypher. It expects to receive the 64-bit
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-- This module implements the DES 56-bit Key Block Cypher. It expects to receive the 64-bit
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-- data block to be encrypted or decrypted on the indata bus, and the 64-bit key on the inKey
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-- data block to be encrypted or decrypted on the indata bus, and the 64-bit key on the inKey
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-- bus. When the DS signal is high, encryption/decryption begins. If the DECIPHER signal is
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-- bus. When the DS signal is high, encryption/decryption begins. If the DECIPHER signal is
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| Line 50... |
Line 53... |
-- cycle, one round of encryption is performed. After 16 rounds, the resulting message block
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-- cycle, one round of encryption is performed. After 16 rounds, the resulting message block
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-- is presented on the OUTDATA bus and the RDY signal is set high.
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-- is presented on the OUTDATA bus and the RDY signal is set high.
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--
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--
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-- Comments, questions and suggestions may be directed to the author at srmcqueen@mcqueentech.com.
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-- Comments, questions and suggestions may be directed to the author at srmcqueen@mcqueentech.com.
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-- 2005/09/02
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-- Optimized key handling
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-- added optional signals, changed RDY to be low on reset
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-- Perttu Fagerlund
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library IEEE;
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-- 2005/10/15
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use IEEE.STD_LOGIC_1164.ALL;
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-- Added comments
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use IEEE.STD_LOGIC_ARITH.ALL;
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-- Steven R. McQueen
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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ENTITY des56 IS
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PORT(
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indata : IN std_logic_vector (0 TO 63);
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inkey : IN std_logic_vector (0 TO 63);
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outdata : OUT std_logic_vector (0 TO 63);
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decipher : IN std_logic;
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ds : IN std_logic;
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clk : IN std_logic;
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rst : IN std_logic;
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rdy_next_next_cycle : OUT std_logic; -- output will be ready in two clock cycles - optional signal
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rdy_next_cycle : OUT std_logic; -- output will be ready in one clock cycle - optional signal
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rdy : OUT std_logic -- output is ready NOW
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);
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entity des56 is
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END des56 ;
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Port ( indata : in std_logic_vector(0 to 63);
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inkey : in std_logic_vector(0 to 63);
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outdata : out std_logic_vector(0 to 63);
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decipher: in std_logic;
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ds : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rdy : out std_logic);
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end des56;
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architecture des of des56 is
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architecture des of des56 is
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-- ***********************************************************
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-- * The following attributes are useful in Xilinx ISE
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-- * for debugging purposes. They have been commented
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-- * out to permit logic optimization.
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-- ***********************************************************
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--attribute keep: string;
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--attribute keep: string;
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--attribute nodelay: string;
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--attribute nodelay: string;
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--attribute s: string;
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--attribute s: string;
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--attribute nodelay of indata: signal is "true";
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--attribute nodelay of indata: signal is "true";
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| Line 98... |
Line 121... |
--attribute s of outdata: signal is "yes";
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--attribute s of outdata: signal is "yes";
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--signal xclk: std_logic;
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--signal xclk: std_logic;
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--attribute keep of xclk: signal is "true";
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--attribute keep of xclk: signal is "true";
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-- These signals hold the round keys - they are loaded on the first clock
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signal K01: std_logic_vector(0 to 47);
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signal K02: std_logic_vector(0 to 47);
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signal K03: std_logic_vector(0 to 47);
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signal K04: std_logic_vector(0 to 47);
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signal K05: std_logic_vector(0 to 47);
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signal K06: std_logic_vector(0 to 47);
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signal K07: std_logic_vector(0 to 47);
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signal K08: std_logic_vector(0 to 47);
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signal K09: std_logic_vector(0 to 47);
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signal K10: std_logic_vector(0 to 47);
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signal K11: std_logic_vector(0 to 47);
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signal K12: std_logic_vector(0 to 47);
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signal K13: std_logic_vector(0 to 47);
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signal K14: std_logic_vector(0 to 47);
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signal K15: std_logic_vector(0 to 47);
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-- mykey and inmsg are inputs to the encryption round logic
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-- mykey and inmsg are inputs to the encryption round logic
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-- they will get new values on each clock
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-- they will get new values on each clock
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-- outmsg is the result of the encryption round, it will become inmsg for the next round
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-- outmsg is the result of the encryption round, it will become inmsg for the next round
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-- there are 16 encryption rounds in DES
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-- there are 16 encryption rounds in DES
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signal mykey: std_logic_vector(0 to 47);
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signal mykey: std_logic_vector(0 to 47);
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| Line 137... |
Line 143... |
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-- the decrypt register holds the decrypt/encrypt switch
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-- the decrypt register holds the decrypt/encrypt switch
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signal decrypt: std_logic;
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signal decrypt: std_logic;
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signal ready: std_logic;
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signal ready: std_logic;
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-- various work signals. I want most of them to be wires, but
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-- **********************************************
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-- they may be registers or latches, depending on the synthesizer
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-- * New key registers.
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-- **********************************************
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signal key_l : std_logic_vector(0 to 27);
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signal key_r : std_logic_vector(0 to 27);
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signal keylr : std_logic_vector(0 to 55);
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-- ******************************************************************
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-- * various work signals. I want most of them to be wires, but
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-- * they may be registers or latches, depending on the synthesizer
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-- ******************************************************************
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signal d: std_logic_vector(0 to 47);
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signal d: std_logic_vector(0 to 47);
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signal f: std_logic_vector(0 to 31);
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signal f: std_logic_vector(0 to 31);
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signal b1: std_logic_vector(0 to 5);
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signal b1: std_logic_vector(0 to 5);
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signal b2: std_logic_vector(0 to 5);
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signal b2: std_logic_vector(0 to 5);
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signal b3: std_logic_vector(0 to 5);
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signal b3: std_logic_vector(0 to 5);
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| Line 158... |
Line 173... |
signal s5: std_logic_vector(0 to 3);
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signal s5: std_logic_vector(0 to 3);
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signal s6: std_logic_vector(0 to 3);
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signal s6: std_logic_vector(0 to 3);
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signal s7: std_logic_vector(0 to 3);
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signal s7: std_logic_vector(0 to 3);
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signal s8: std_logic_vector(0 to 3);
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signal s8: std_logic_vector(0 to 3);
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begin
|
begin
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-- Register Input Data
|
-- ***************************************************************************************************
|
--
|
-- * Route wires to copy the key value for the next encryption round
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-- When data strobe is high and clock is on the rising edge,
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-- ***************************************************************************************************
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-- load the round key registers.
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keylr <= key_l & key_r;
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RegData: process (clk, ds, decipher)
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mykey <= keylr(13) & keylr(16) & keylr(10) & keylr(23) & keylr(0) & keylr(4) & keylr(2) & keylr(27) &
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keylr(14) & keylr(5) & keylr(20) & keylr(9) & keylr(22) & keylr(18) & keylr(11) & keylr(3) &
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begin
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keylr(25) & keylr(7) & keylr(15) & keylr(6) & keylr(26) & keylr(19) & keylr(12) & keylr(1) &
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keylr(40) & keylr(51) & keylr(30) & keylr(36) & keylr(46) & keylr(54) & keylr(29) & keylr(39) &
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if rising_edge(clk) then
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keylr(50) & keylr(44) & keylr(32) & keylr(47) & keylr(43) & keylr(48) & keylr(38) & keylr(55) &
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if ds = '1' then
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keylr(33) & keylr(52) & keylr(45) & keylr(41) & keylr(49) & keylr(35) & keylr(28) & keylr(31);
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if decipher = '1' then
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K15 <=
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inkey(9) & inkey(50) & inkey(33) & inkey(59) & inkey(48) & inkey(16) & inkey(32) & inkey(56) &
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inkey(1) & inkey(8) & inkey(18) & inkey(41) & inkey(2) & inkey(34) & inkey(25) & inkey(24) &
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inkey(43) & inkey(57) & inkey(58) & inkey(0) & inkey(35) & inkey(26) & inkey(17) & inkey(40) &
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inkey(21) & inkey(27) & inkey(38) & inkey(53) & inkey(36) & inkey(3) & inkey(46) & inkey(29) &
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inkey(4) & inkey(52) & inkey(22) & inkey(28) & inkey(60) & inkey(20) & inkey(37) & inkey(62) &
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inkey(14) & inkey(19) & inkey(44) & inkey(13) & inkey(12) & inkey(61) & inkey(54) & inkey(30);
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K14 <=
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inkey(1) & inkey(42) & inkey(25) & inkey(51) & inkey(40) & inkey(8) & inkey(24) & inkey(48) &
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inkey(58) & inkey(0) & inkey(10) & inkey(33) & inkey(59) & inkey(26) & inkey(17) & inkey(16) &
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inkey(35) & inkey(49) & inkey(50) & inkey(57) & inkey(56) & inkey(18) & inkey(9) & inkey(32) &
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inkey(13) & inkey(19) & inkey(30) & inkey(45) & inkey(28) & inkey(62) & inkey(38) & inkey(21) &
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inkey(27) & inkey(44) & inkey(14) & inkey(20) & inkey(52) & inkey(12) & inkey(29) & inkey(54) &
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inkey(6) & inkey(11) & inkey(36) & inkey(5) & inkey(4) & inkey(53) & inkey(46) & inkey(22);
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K13 <=
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inkey(50) & inkey(26) & inkey(9) & inkey(35) & inkey(24) & inkey(57) & inkey(8) & inkey(32) &
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inkey(42) & inkey(49) & inkey(59) & inkey(17) & inkey(43) & inkey(10) & inkey(1) & inkey(0) &
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inkey(48) & inkey(33) & inkey(34) & inkey(41) & inkey(40) & inkey(2) & inkey(58) & inkey(16) &
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inkey(60) & inkey(3) & inkey(14) & inkey(29) & inkey(12) & inkey(46) & inkey(22) & inkey(5) &
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inkey(11) & inkey(28) & inkey(61) & inkey(4) & inkey(36) & inkey(27) & inkey(13) & inkey(38) &
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inkey(53) & inkey(62) & inkey(20) & inkey(52) & inkey(19) & inkey(37) & inkey(30) & inkey(6);
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K12 <=
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inkey(34) & inkey(10) & inkey(58) & inkey(48) & inkey(8) & inkey(41) & inkey(57) & inkey(16) &
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inkey(26) & inkey(33) & inkey(43) & inkey(1) & inkey(56) & inkey(59) & inkey(50) & inkey(49) &
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inkey(32) & inkey(17) & inkey(18) & inkey(25) & inkey(24) & inkey(51) & inkey(42) & inkey(0) &
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inkey(44) & inkey(54) & inkey(61) & inkey(13) & inkey(27) & inkey(30) & inkey(6) & inkey(52) &
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inkey(62) & inkey(12) & inkey(45) & inkey(19) & inkey(20) & inkey(11) & inkey(60) & inkey(22) &
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inkey(37) & inkey(46) & inkey(4) & inkey(36) & inkey(3) & inkey(21) & inkey(14) & inkey(53);
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K11 <=
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inkey(18) & inkey(59) & inkey(42) & inkey(32) & inkey(57) & inkey(25) & inkey(41) & inkey(0) &
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inkey(10) & inkey(17) & inkey(56) & inkey(50) & inkey(40) & inkey(43) & inkey(34) & inkey(33) &
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inkey(16) & inkey(1) & inkey(2) & inkey(9) & inkey(8) & inkey(35) & inkey(26) & inkey(49) &
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inkey(28) & inkey(38) & inkey(45) & inkey(60) & inkey(11) & inkey(14) & inkey(53) & inkey(36) &
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inkey(46) & inkey(27) & inkey(29) & inkey(3) & inkey(4) & inkey(62) & inkey(44) & inkey(6) &
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inkey(21) & inkey(30) & inkey(19) & inkey(20) & inkey(54) & inkey(5) & inkey(61) & inkey(37);
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K10 <=
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inkey(2) & inkey(43) & inkey(26) & inkey(16) & inkey(41) & inkey(9) & inkey(25) & inkey(49) &
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inkey(59) & inkey(1) & inkey(40) & inkey(34) & inkey(24) & inkey(56) & inkey(18) & inkey(17) &
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inkey(0) & inkey(50) & inkey(51) & inkey(58) & inkey(57) & inkey(48) & inkey(10) & inkey(33) &
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inkey(12) & inkey(22) & inkey(29) & inkey(44) & inkey(62) & inkey(61) & inkey(37) & inkey(20) &
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inkey(30) & inkey(11) & inkey(13) & inkey(54) & inkey(19) & inkey(46) & inkey(28) & inkey(53) &
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inkey(5) & inkey(14) & inkey(3) & inkey(4) & inkey(38) & inkey(52) & inkey(45) & inkey(21);
|
|
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K09 <=
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inkey(51) & inkey(56) & inkey(10) & inkey(0) & inkey(25) & inkey(58) & inkey(9) & inkey(33) &
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inkey(43) & inkey(50) & inkey(24) & inkey(18) & inkey(8) & inkey(40) & inkey(2) & inkey(1) &
|
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inkey(49) & inkey(34) & inkey(35) & inkey(42) & inkey(41) & inkey(32) & inkey(59) & inkey(17) &
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inkey(27) & inkey(6) & inkey(13) & inkey(28) & inkey(46) & inkey(45) & inkey(21) & inkey(4) &
|
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inkey(14) & inkey(62) & inkey(60) & inkey(38) & inkey(3) & inkey(30) & inkey(12) & inkey(37) &
|
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inkey(52) & inkey(61) & inkey(54) & inkey(19) & inkey(22) & inkey(36) & inkey(29) & inkey(5);
|
|
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K08 <=
|
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inkey(35) & inkey(40) & inkey(59) & inkey(49) & inkey(9) & inkey(42) & inkey(58) & inkey(17) &
|
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inkey(56) & inkey(34) & inkey(8) & inkey(2) & inkey(57) & inkey(24) & inkey(51) & inkey(50) &
|
|
inkey(33) & inkey(18) & inkey(48) & inkey(26) & inkey(25) & inkey(16) & inkey(43) & inkey(1) &
|
|
inkey(11) & inkey(53) & inkey(60) & inkey(12) & inkey(30) & inkey(29) & inkey(5) & inkey(19) &
|
|
inkey(61) & inkey(46) & inkey(44) & inkey(22) & inkey(54) & inkey(14) & inkey(27) & inkey(21) &
|
|
inkey(36) & inkey(45) & inkey(38) & inkey(3) & inkey(6) & inkey(20) & inkey(13) & inkey(52);
|
|
|
|
K07 <=
|
|
inkey(56) & inkey(32) & inkey(51) & inkey(41) & inkey(1) & inkey(34) & inkey(50) & inkey(9) &
|
|
inkey(48) & inkey(26) & inkey(0) & inkey(59) & inkey(49) & inkey(16) & inkey(43) & inkey(42) &
|
|
inkey(25) & inkey(10) & inkey(40) & inkey(18) & inkey(17) & inkey(8) & inkey(35) & inkey(58) &
|
|
inkey(3) & inkey(45) & inkey(52) & inkey(4) & inkey(22) & inkey(21) & inkey(60) & inkey(11) &
|
|
inkey(53) & inkey(38) & inkey(36) & inkey(14) & inkey(46) & inkey(6) & inkey(19) & inkey(13) &
|
|
inkey(28) & inkey(37) & inkey(30) & inkey(62) & inkey(61) & inkey(12) & inkey(5) & inkey(44);
|
|
|
|
K06 <=
|
|
inkey(40) & inkey(16) & inkey(35) & inkey(25) & inkey(50) & inkey(18) & inkey(34) & inkey(58) &
|
|
inkey(32) & inkey(10) & inkey(49) & inkey(43) & inkey(33) & inkey(0) & inkey(56) & inkey(26) &
|
|
inkey(9) & inkey(59) & inkey(24) & inkey(2) & inkey(1) & inkey(57) & inkey(48) & inkey(42) &
|
|
inkey(54) & inkey(29) & inkey(36) & inkey(19) & inkey(6) & inkey(5) & inkey(44) & inkey(62) &
|
|
inkey(37) & inkey(22) & inkey(20) & inkey(61) & inkey(30) & inkey(53) & inkey(3) & inkey(60) &
|
|
inkey(12) & inkey(21) & inkey(14) & inkey(46) & inkey(45) & inkey(27) & inkey(52) & inkey(28);
|
|
|
|
K05 <=
|
|
inkey(24) & inkey(0) & inkey(48) & inkey(9) & inkey(34) & inkey(2) & inkey(18) & inkey(42) &
|
|
inkey(16) & inkey(59) & inkey(33) & inkey(56) & inkey(17) & inkey(49) & inkey(40) & inkey(10) &
|
|
inkey(58) & inkey(43) & inkey(8) & inkey(51) & inkey(50) & inkey(41) & inkey(32) & inkey(26) &
|
|
inkey(38) & inkey(13) & inkey(20) & inkey(3) & inkey(53) & inkey(52) & inkey(28) & inkey(46) &
|
|
inkey(21) & inkey(6) & inkey(4) & inkey(45) & inkey(14) & inkey(37) & inkey(54) & inkey(44) &
|
|
inkey(27) & inkey(5) & inkey(61) & inkey(30) & inkey(29) & inkey(11) & inkey(36) & inkey(12);
|
|
|
|
K04 <=
|
|
inkey(8) & inkey(49) & inkey(32) & inkey(58) & inkey(18) & inkey(51) & inkey(2) & inkey(26) &
|
|
inkey(0) & inkey(43) & inkey(17) & inkey(40) & inkey(1) & inkey(33) & inkey(24) & inkey(59) &
|
|
inkey(42) & inkey(56) & inkey(57) & inkey(35) & inkey(34) & inkey(25) & inkey(16) & inkey(10) &
|
|
inkey(22) & inkey(60) & inkey(4) & inkey(54) & inkey(37) & inkey(36) & inkey(12) & inkey(30) &
|
|
inkey(5) & inkey(53) & inkey(19) & inkey(29) & inkey(61) & inkey(21) & inkey(38) & inkey(28) &
|
|
inkey(11) & inkey(52) & inkey(45) & inkey(14) & inkey(13) & inkey(62) & inkey(20) & inkey(27);
|
|
|
|
K03 <=
|
|
inkey(57) & inkey(33) & inkey(16) & inkey(42) & inkey(2) & inkey(35) & inkey(51) & inkey(10) &
|
|
inkey(49) & inkey(56) & inkey(1) & inkey(24) & inkey(50) & inkey(17) & inkey(8) & inkey(43) &
|
|
inkey(26) & inkey(40) & inkey(41) & inkey(48) & inkey(18) & inkey(9) & inkey(0) & inkey(59) &
|
|
inkey(6) & inkey(44) & inkey(19) & inkey(38) & inkey(21) & inkey(20) & inkey(27) & inkey(14) &
|
|
inkey(52) & inkey(37) & inkey(3) & inkey(13) & inkey(45) & inkey(5) & inkey(22) & inkey(12) &
|
|
inkey(62) & inkey(36) & inkey(29) & inkey(61) & inkey(60) & inkey(46) & inkey(4) & inkey(11);
|
|
|
|
K02 <=
|
|
inkey(41) & inkey(17) & inkey(0) & inkey(26) & inkey(51) & inkey(48) & inkey(35) & inkey(59) &
|
|
inkey(33) & inkey(40) & inkey(50) & inkey(8) & inkey(34) & inkey(1) & inkey(57) & inkey(56) &
|
|
inkey(10) & inkey(24) & inkey(25) & inkey(32) & inkey(2) & inkey(58) & inkey(49) & inkey(43) &
|
|
inkey(53) & inkey(28) & inkey(3) & inkey(22) & inkey(5) & inkey(4) & inkey(11) & inkey(61) &
|
|
inkey(36) & inkey(21) & inkey(54) & inkey(60) & inkey(29) & inkey(52) & inkey(6) & inkey(27) &
|
|
inkey(46) & inkey(20) & inkey(13) & inkey(45) & inkey(44) & inkey(30) & inkey(19) & inkey(62);
|
|
|
|
K01 <=
|
|
inkey(25) & inkey(1) & inkey(49) & inkey(10) & inkey(35) & inkey(32) & inkey(48) & inkey(43) &
|
|
inkey(17) & inkey(24) & inkey(34) & inkey(57) & inkey(18) & inkey(50) & inkey(41) & inkey(40) &
|
|
inkey(59) & inkey(8) & inkey(9) & inkey(16) & inkey(51) & inkey(42) & inkey(33) & inkey(56) &
|
|
inkey(37) & inkey(12) & inkey(54) & inkey(6) & inkey(52) & inkey(19) & inkey(62) & inkey(45) &
|
|
inkey(20) & inkey(5) & inkey(38) & inkey(44) & inkey(13) & inkey(36) & inkey(53) & inkey(11) &
|
|
inkey(30) & inkey(4) & inkey(60) & inkey(29) & inkey(28) & inkey(14) & inkey(3) & inkey(46);
|
|
|
|
else
|
|
|
|
K01 <=
|
|
inkey(1) & inkey(42) & inkey(25) & inkey(51) & inkey(40) & inkey(8) & inkey(24) & inkey(48) &
|
|
inkey(58) & inkey(0) & inkey(10) & inkey(33) & inkey(59) & inkey(26) & inkey(17) & inkey(16) &
|
|
inkey(35) & inkey(49) & inkey(50) & inkey(57) & inkey(56) & inkey(18) & inkey(9) & inkey(32) &
|
|
inkey(13) & inkey(19) & inkey(30) & inkey(45) & inkey(28) & inkey(62) & inkey(38) & inkey(21) &
|
|
inkey(27) & inkey(44) & inkey(14) & inkey(20) & inkey(52) & inkey(12) & inkey(29) & inkey(54) &
|
|
inkey(6) & inkey(11) & inkey(36) & inkey(5) & inkey(4) & inkey(53) & inkey(46) & inkey(22);
|
|
|
|
K02 <=
|
|
inkey(50) & inkey(26) & inkey(9) & inkey(35) & inkey(24) & inkey(57) & inkey(8) & inkey(32) &
|
|
inkey(42) & inkey(49) & inkey(59) & inkey(17) & inkey(43) & inkey(10) & inkey(1) & inkey(0) &
|
|
inkey(48) & inkey(33) & inkey(34) & inkey(41) & inkey(40) & inkey(2) & inkey(58) & inkey(16) &
|
|
inkey(60) & inkey(3) & inkey(14) & inkey(29) & inkey(12) & inkey(46) & inkey(22) & inkey(5) &
|
|
inkey(11) & inkey(28) & inkey(61) & inkey(4) & inkey(36) & inkey(27) & inkey(13) & inkey(38) &
|
|
inkey(53) & inkey(62) & inkey(20) & inkey(52) & inkey(19) & inkey(37) & inkey(30) & inkey(6);
|
|
|
|
K03 <=
|
|
inkey(34) & inkey(10) & inkey(58) & inkey(48) & inkey(8) & inkey(41) & inkey(57) & inkey(16) &
|
|
inkey(26) & inkey(33) & inkey(43) & inkey(1) & inkey(56) & inkey(59) & inkey(50) & inkey(49) &
|
|
inkey(32) & inkey(17) & inkey(18) & inkey(25) & inkey(24) & inkey(51) & inkey(42) & inkey(0) &
|
|
inkey(44) & inkey(54) & inkey(61) & inkey(13) & inkey(27) & inkey(30) & inkey(6) & inkey(52) &
|
|
inkey(62) & inkey(12) & inkey(45) & inkey(19) & inkey(20) & inkey(11) & inkey(60) & inkey(22) &
|
|
inkey(37) & inkey(46) & inkey(4) & inkey(36) & inkey(3) & inkey(21) & inkey(14) & inkey(53);
|
|
|
|
K04 <=
|
|
inkey(18) & inkey(59) & inkey(42) & inkey(32) & inkey(57) & inkey(25) & inkey(41) & inkey(0) &
|
|
inkey(10) & inkey(17) & inkey(56) & inkey(50) & inkey(40) & inkey(43) & inkey(34) & inkey(33) &
|
|
inkey(16) & inkey(1) & inkey(2) & inkey(9) & inkey(8) & inkey(35) & inkey(26) & inkey(49) &
|
|
inkey(28) & inkey(38) & inkey(45) & inkey(60) & inkey(11) & inkey(14) & inkey(53) & inkey(36) &
|
|
inkey(46) & inkey(27) & inkey(29) & inkey(3) & inkey(4) & inkey(62) & inkey(44) & inkey(6) &
|
|
inkey(21) & inkey(30) & inkey(19) & inkey(20) & inkey(54) & inkey(5) & inkey(61) & inkey(37);
|
|
|
|
K05 <=
|
|
inkey(2) & inkey(43) & inkey(26) & inkey(16) & inkey(41) & inkey(9) & inkey(25) & inkey(49) &
|
|
inkey(59) & inkey(1) & inkey(40) & inkey(34) & inkey(24) & inkey(56) & inkey(18) & inkey(17) &
|
|
inkey(0) & inkey(50) & inkey(51) & inkey(58) & inkey(57) & inkey(48) & inkey(10) & inkey(33) &
|
|
inkey(12) & inkey(22) & inkey(29) & inkey(44) & inkey(62) & inkey(61) & inkey(37) & inkey(20) &
|
|
inkey(30) & inkey(11) & inkey(13) & inkey(54) & inkey(19) & inkey(46) & inkey(28) & inkey(53) &
|
|
inkey(5) & inkey(14) & inkey(3) & inkey(4) & inkey(38) & inkey(52) & inkey(45) & inkey(21);
|
|
|
|
K06 <=
|
|
inkey(51) & inkey(56) & inkey(10) & inkey(0) & inkey(25) & inkey(58) & inkey(9) & inkey(33) &
|
|
inkey(43) & inkey(50) & inkey(24) & inkey(18) & inkey(8) & inkey(40) & inkey(2) & inkey(1) &
|
|
inkey(49) & inkey(34) & inkey(35) & inkey(42) & inkey(41) & inkey(32) & inkey(59) & inkey(17) &
|
|
inkey(27) & inkey(6) & inkey(13) & inkey(28) & inkey(46) & inkey(45) & inkey(21) & inkey(4) &
|
|
inkey(14) & inkey(62) & inkey(60) & inkey(38) & inkey(3) & inkey(30) & inkey(12) & inkey(37) &
|
|
inkey(52) & inkey(61) & inkey(54) & inkey(19) & inkey(22) & inkey(36) & inkey(29) & inkey(5);
|
|
|
|
K07 <=
|
|
inkey(35) & inkey(40) & inkey(59) & inkey(49) & inkey(9) & inkey(42) & inkey(58) & inkey(17) &
|
|
inkey(56) & inkey(34) & inkey(8) & inkey(2) & inkey(57) & inkey(24) & inkey(51) & inkey(50) &
|
|
inkey(33) & inkey(18) & inkey(48) & inkey(26) & inkey(25) & inkey(16) & inkey(43) & inkey(1) &
|
|
inkey(11) & inkey(53) & inkey(60) & inkey(12) & inkey(30) & inkey(29) & inkey(5) & inkey(19) &
|
|
inkey(61) & inkey(46) & inkey(44) & inkey(22) & inkey(54) & inkey(14) & inkey(27) & inkey(21) &
|
|
inkey(36) & inkey(45) & inkey(38) & inkey(3) & inkey(6) & inkey(20) & inkey(13) & inkey(52);
|
|
|
|
K08 <=
|
|
inkey(56) & inkey(32) & inkey(51) & inkey(41) & inkey(1) & inkey(34) & inkey(50) & inkey(9) &
|
|
inkey(48) & inkey(26) & inkey(0) & inkey(59) & inkey(49) & inkey(16) & inkey(43) & inkey(42) &
|
|
inkey(25) & inkey(10) & inkey(40) & inkey(18) & inkey(17) & inkey(8) & inkey(35) & inkey(58) &
|
|
inkey(3) & inkey(45) & inkey(52) & inkey(4) & inkey(22) & inkey(21) & inkey(60) & inkey(11) &
|
|
inkey(53) & inkey(38) & inkey(36) & inkey(14) & inkey(46) & inkey(6) & inkey(19) & inkey(13) &
|
|
inkey(28) & inkey(37) & inkey(30) & inkey(62) & inkey(61) & inkey(12) & inkey(5) & inkey(44);
|
|
|
|
K09 <=
|
|
inkey(40) & inkey(16) & inkey(35) & inkey(25) & inkey(50) & inkey(18) & inkey(34) & inkey(58) &
|
|
inkey(32) & inkey(10) & inkey(49) & inkey(43) & inkey(33) & inkey(0) & inkey(56) & inkey(26) &
|
|
inkey(9) & inkey(59) & inkey(24) & inkey(2) & inkey(1) & inkey(57) & inkey(48) & inkey(42) &
|
|
inkey(54) & inkey(29) & inkey(36) & inkey(19) & inkey(6) & inkey(5) & inkey(44) & inkey(62) &
|
|
inkey(37) & inkey(22) & inkey(20) & inkey(61) & inkey(30) & inkey(53) & inkey(3) & inkey(60) &
|
|
inkey(12) & inkey(21) & inkey(14) & inkey(46) & inkey(45) & inkey(27) & inkey(52) & inkey(28);
|
|
|
|
K10 <=
|
|
inkey(24) & inkey(0) & inkey(48) & inkey(9) & inkey(34) & inkey(2) & inkey(18) & inkey(42) &
|
|
inkey(16) & inkey(59) & inkey(33) & inkey(56) & inkey(17) & inkey(49) & inkey(40) & inkey(10) &
|
|
inkey(58) & inkey(43) & inkey(8) & inkey(51) & inkey(50) & inkey(41) & inkey(32) & inkey(26) &
|
|
inkey(38) & inkey(13) & inkey(20) & inkey(3) & inkey(53) & inkey(52) & inkey(28) & inkey(46) &
|
|
inkey(21) & inkey(6) & inkey(4) & inkey(45) & inkey(14) & inkey(37) & inkey(54) & inkey(44) &
|
|
inkey(27) & inkey(5) & inkey(61) & inkey(30) & inkey(29) & inkey(11) & inkey(36) & inkey(12);
|
|
|
|
K11 <=
|
|
inkey(8) & inkey(49) & inkey(32) & inkey(58) & inkey(18) & inkey(51) & inkey(2) & inkey(26) &
|
|
inkey(0) & inkey(43) & inkey(17) & inkey(40) & inkey(1) & inkey(33) & inkey(24) & inkey(59) &
|
|
inkey(42) & inkey(56) & inkey(57) & inkey(35) & inkey(34) & inkey(25) & inkey(16) & inkey(10) &
|
|
inkey(22) & inkey(60) & inkey(4) & inkey(54) & inkey(37) & inkey(36) & inkey(12) & inkey(30) &
|
|
inkey(5) & inkey(53) & inkey(19) & inkey(29) & inkey(61) & inkey(21) & inkey(38) & inkey(28) &
|
|
inkey(11) & inkey(52) & inkey(45) & inkey(14) & inkey(13) & inkey(62) & inkey(20) & inkey(27);
|
|
|
|
K12 <=
|
|
inkey(57) & inkey(33) & inkey(16) & inkey(42) & inkey(2) & inkey(35) & inkey(51) & inkey(10) &
|
|
inkey(49) & inkey(56) & inkey(1) & inkey(24) & inkey(50) & inkey(17) & inkey(8) & inkey(43) &
|
|
inkey(26) & inkey(40) & inkey(41) & inkey(48) & inkey(18) & inkey(9) & inkey(0) & inkey(59) &
|
|
inkey(6) & inkey(44) & inkey(19) & inkey(38) & inkey(21) & inkey(20) & inkey(27) & inkey(14) &
|
|
inkey(52) & inkey(37) & inkey(3) & inkey(13) & inkey(45) & inkey(5) & inkey(22) & inkey(12) &
|
|
inkey(62) & inkey(36) & inkey(29) & inkey(61) & inkey(60) & inkey(46) & inkey(4) & inkey(11);
|
|
|
|
K13 <=
|
|
inkey(41) & inkey(17) & inkey(0) & inkey(26) & inkey(51) & inkey(48) & inkey(35) & inkey(59) &
|
|
inkey(33) & inkey(40) & inkey(50) & inkey(8) & inkey(34) & inkey(1) & inkey(57) & inkey(56) &
|
|
inkey(10) & inkey(24) & inkey(25) & inkey(32) & inkey(2) & inkey(58) & inkey(49) & inkey(43) &
|
|
inkey(53) & inkey(28) & inkey(3) & inkey(22) & inkey(5) & inkey(4) & inkey(11) & inkey(61) &
|
|
inkey(36) & inkey(21) & inkey(54) & inkey(60) & inkey(29) & inkey(52) & inkey(6) & inkey(27) &
|
|
inkey(46) & inkey(20) & inkey(13) & inkey(45) & inkey(44) & inkey(30) & inkey(19) & inkey(62);
|
|
|
|
K14 <=
|
|
inkey(25) & inkey(1) & inkey(49) & inkey(10) & inkey(35) & inkey(32) & inkey(48) & inkey(43) &
|
|
inkey(17) & inkey(24) & inkey(34) & inkey(57) & inkey(18) & inkey(50) & inkey(41) & inkey(40) &
|
|
inkey(59) & inkey(8) & inkey(9) & inkey(16) & inkey(51) & inkey(42) & inkey(33) & inkey(56) &
|
|
inkey(37) & inkey(12) & inkey(54) & inkey(6) & inkey(52) & inkey(19) & inkey(62) & inkey(45) &
|
|
inkey(20) & inkey(5) & inkey(38) & inkey(44) & inkey(13) & inkey(36) & inkey(53) & inkey(11) &
|
|
inkey(30) & inkey(4) & inkey(60) & inkey(29) & inkey(28) & inkey(14) & inkey(3) & inkey(46);
|
|
|
|
K15 <=
|
|
inkey(17) & inkey(58) & inkey(41) & inkey(2) & inkey(56) & inkey(24) & inkey(40) & inkey(35) &
|
|
inkey(9) & inkey(16) & inkey(26) & inkey(49) & inkey(10) & inkey(42) & inkey(33) & inkey(32) &
|
|
inkey(51) & inkey(0) & inkey(1) & inkey(8) & inkey(43) & inkey(34) & inkey(25) & inkey(48) &
|
|
inkey(29) & inkey(4) & inkey(46) & inkey(61) & inkey(44) & inkey(11) & inkey(54) & inkey(37) &
|
|
inkey(12) & inkey(60) & inkey(30) & inkey(36) & inkey(5) & inkey(28) & inkey(45) & inkey(3) &
|
|
inkey(22) & inkey(27) & inkey(52) & inkey(21) & inkey(20) & inkey(6) & inkey(62) & inkey(38);
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process RegData;
|
|
|
|
|
|
-- Select the key value for the next encryption round
|
|
-- Use the current value of COUNTUP to determine which round of encryption is next.
|
|
-- Load the MYKEY register with the appropriate round key value.
|
|
-- Note that on the first pass, the round key is not available, and must be
|
|
-- loaded directly from the input signals. The correct value is determined by
|
|
-- the state of the DECIPHER signal.
|
|
SetKey: process (clk, countup, decipher)
|
SetKey: process (clk, countup, decipher)
|
-- NOTE: according to ModelSim, the output value of some of these multiplexers
|
-- *********************************************************************************************
|
-- is not stable for enough time before the clock is propagated. What can I do
|
-- * New key management logic by Perttu Fagerlund
|
-- about that?
|
-- * On the first clock, the first round key is registered. Thereafter, the round key is simply
|
|
-- * shifted by the necessary number of bits. This saves more than 57% of the required register
|
|
-- * logic cells over the previous code, which directly registered all of the round keys at once.
|
|
-- *
|
|
-- * A very slight speed increase may be realized due to shorter signal paths in the final fit.
|
|
-- *
|
|
-- * Use the current value of COUNTUP to determine which round of encryption is next.
|
|
-- * Load the KEY_L and KEY_R registers with the appropriate round key value.
|
|
-- * Note that on the first pass, the round key is not available, and must be
|
|
-- * loaded directly from the input signals. The correct value is determined by
|
|
-- * the state of the DECIPHER signal.
|
|
-- *********************************************************************************************
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
case countup is
|
case countup is
|
when 0 =>
|
when 0 =>
|
if decipher = '1' then
|
if (decipher = '0') then
|
mykey <=
|
-- these are readily shifted left by one !
|
inkey(17) & inkey(58) & inkey(41) & inkey(2) & inkey(56) & inkey(24) & inkey(40) & inkey(35) &
|
key_l <= inkey(48) & inkey(40) & inkey(32) & inkey(24) & inkey(16) & inkey(8) & inkey(0) &
|
inkey(9) & inkey(16) & inkey(26) & inkey(49) & inkey(10) & inkey(42) & inkey(33) & inkey(32) &
|
inkey(57) & inkey(49) & inkey(41) & inkey(33) & inkey(25) & inkey(17) & inkey(9) & inkey(1) &
|
inkey(51) & inkey(0) & inkey(1) & inkey(8) & inkey(43) & inkey(34) & inkey(25) & inkey(48) &
|
inkey(58) & inkey(50) & inkey(42) & inkey(34) & inkey(26) & inkey(18) & inkey(10) & inkey(2) &
|
inkey(29) & inkey(4) & inkey(46) & inkey(61) & inkey(44) & inkey(11) & inkey(54) & inkey(37) &
|
inkey(59) & inkey(51) & inkey(43) & inkey(35) & inkey(56);
|
inkey(12) & inkey(60) & inkey(30) & inkey(36) & inkey(5) & inkey(28) & inkey(45) & inkey(3) &
|
key_r <= inkey(54) & inkey(46) & inkey(38) & inkey(30) & inkey(22) & inkey(14) & inkey(6) &
|
inkey(22) & inkey(27) & inkey(52) & inkey(21) & inkey(20) & inkey(6) & inkey(62) & inkey(38);
|
inkey(61) & inkey(53) & inkey(45) & inkey(37) & inkey(29) & inkey(21) & inkey(13) & inkey(5) &
|
|
inkey(60) & inkey(52) & inkey(44) & inkey(36) & inkey(28) & inkey(20) & inkey(12) & inkey(4) &
|
|
inkey(27) & inkey(19) & inkey(11) & inkey(3) & inkey(62);
|
else
|
else
|
mykey <=
|
key_l <= inkey(56) & inkey(48) & inkey(40) & inkey(32) & inkey(24) & inkey(16) & inkey(8) & inkey(0) &
|
inkey(9) & inkey(50) & inkey(33) & inkey(59) & inkey(48) & inkey(16) & inkey(32) & inkey(56) &
|
inkey(57) & inkey(49) & inkey(41) & inkey(33) & inkey(25) & inkey(17) & inkey(9) & inkey(1) &
|
inkey(1) & inkey(8) & inkey(18) & inkey(41) & inkey(2) & inkey(34) & inkey(25) & inkey(24) &
|
inkey(58) & inkey(50) & inkey(42) & inkey(34) & inkey(26) & inkey(18) & inkey(10) & inkey(2) &
|
inkey(43) & inkey(57) & inkey(58) & inkey(0) & inkey(35) & inkey(26) & inkey(17) & inkey(40) &
|
inkey(59) & inkey(51) & inkey(43) & inkey(35);
|
inkey(21) & inkey(27) & inkey(38) & inkey(53) & inkey(36) & inkey(3) & inkey(46) & inkey(29) &
|
key_r <= inkey(62) & inkey(54) & inkey(46) & inkey(38) & inkey(30) & inkey(22) & inkey(14) & inkey(6) &
|
inkey(4) & inkey(52) & inkey(22) & inkey(28) & inkey(60) & inkey(20) & inkey(37) & inkey(62) &
|
inkey(61) & inkey(53) & inkey(45) & inkey(37) & inkey(29) & inkey(21) & inkey(13) & inkey(5) &
|
inkey(14) & inkey(19) & inkey(44) & inkey(13) & inkey(12) & inkey(61) & inkey(54) & inkey(30);
|
inkey(60) & inkey(52) & inkey(44) & inkey(36) & inkey(28) & inkey(20) & inkey(12) & inkey(4) &
|
|
inkey(27) & inkey(19) & inkey(11) & inkey(3);
|
end if;
|
end if;
|
|
|
when 1 =>
|
when 1 =>
|
mykey <= K01;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(27) & key_l(0 to 26);
|
|
key_r(0 to 27) <= key_r(27) & key_r(0 to 26);
|
|
else
|
|
key_l(0 to 27) <= key_l(1 to 27) & key_l(0);
|
|
key_r(0 to 27) <= key_r(1 to 27) & key_r(0);
|
|
end if;
|
when 2 =>
|
when 2 =>
|
mykey <= K02;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 3 =>
|
when 3 =>
|
mykey <= K03;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 4 =>
|
when 4 =>
|
mykey <= K04;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 5 =>
|
when 5 =>
|
mykey <= K05;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 6 =>
|
when 6 =>
|
mykey <= K06;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 7 =>
|
when 7 =>
|
mykey <= K07;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 8 =>
|
when 8 =>
|
mykey <= K08;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(27) & key_l(0 to 26);
|
|
key_r(0 to 27) <= key_r(27) & key_r(0 to 26);
|
|
else
|
|
key_l(0 to 27) <= key_l(1 to 27) & key_l(0);
|
|
key_r(0 to 27) <= key_r(1 to 27) & key_r(0);
|
|
end if;
|
when 9 =>
|
when 9 =>
|
mykey <= K09;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 10 =>
|
when 10 =>
|
mykey <= K10;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 11 =>
|
when 11 =>
|
mykey <= K11;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 12 =>
|
when 12 =>
|
mykey <= K12;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 13 =>
|
when 13 =>
|
mykey <= K13;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 14 =>
|
when 14 =>
|
mykey <= K14;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
|
|
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
|
|
else
|
|
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
|
|
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
|
|
end if;
|
when 15 =>
|
when 15 =>
|
mykey <= K15;
|
if (decipher = '1') then
|
|
key_l(0 to 27) <= key_l(27) & key_l(0 to 26);
|
|
key_r(0 to 27) <= key_r(27) & key_r(0 to 26);
|
|
else
|
|
key_l(0 to 27) <= key_l(1 to 27) & key_l(0);
|
|
key_r(0 to 27) <= key_r(1 to 27) & key_r(0);
|
|
end if;
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
end process SetKey;
|
end process SetKey;
|
|
|
|
|
-- Load the message word for the next encryption round
|
|
-- As in SetKey, the data must be taken from the input ports on the first round.
|
-- **********************************************************************************************
|
-- For all other rounds, the data value is taken from the OUTMSG signal. This signal
|
-- * Load the message word for the next encryption round
|
-- is produced by combinatorial logic.
|
-- * As in SetKey, the data must be taken from the input ports on the first round.
|
--
|
-- * For all other rounds, the data value is taken from the OUTMSG signal. This signal
|
-- The first round of this cycle can be the last round of the previous cycle. Output is
|
-- * is produced by combinatorial logic.
|
-- driven at this time.
|
-- *
|
|
-- * The first round of this cycle can be the last round of the previous cycle. Output is
|
|
-- * driven at this time.
|
|
-- **********************************************************************************************
|
SetData: process (clk, countup, rst, ds)
|
SetData: process (clk, countup, rst, ds)
|
variable C17: std_logic_vector(1 to 64);
|
variable C17: std_logic_vector(1 to 64);
|
begin
|
begin
|
if rst = '1' then
|
if rst = '1' then
|
rdy <= '1';
|
-- rdy <= '1'; -- Original implementation - rdy is set high at reset
|
|
rdy <= '0'; -- Optional implementation - rdy is set low at reset
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
-- NOTE: INMSG is driven by a multiplexer. It seems that the output signal
|
rdy <= '0';
|
-- for this mux is not always stable before the clock is propagated. Same
|
|
-- problem as above. Should I be using another construct?
|
|
case countup is
|
case countup is
|
when 0 =>
|
when 0 =>
|
if ds = '1' then
|
if ds = '1' then
|
|
-- new data: clock INMSG values directly from input signal
|
inmsg <= indata(57) & indata(49) & indata(41) & indata(33) & indata(25) & indata(17) & indata(9) & indata(1) &
|
inmsg <= indata(57) & indata(49) & indata(41) & indata(33) & indata(25) & indata(17) & indata(9) & indata(1) &
|
indata(59) & indata(51) & indata(43) & indata(35) & indata(27) & indata(19) & indata(11) & indata(3) &
|
indata(59) & indata(51) & indata(43) & indata(35) & indata(27) & indata(19) & indata(11) & indata(3) &
|
indata(61) & indata(53) & indata(45) & indata(37) & indata(29) & indata(21) & indata(13) & indata(5) &
|
indata(61) & indata(53) & indata(45) & indata(37) & indata(29) & indata(21) & indata(13) & indata(5) &
|
indata(63) & indata(55) & indata(47) & indata(39) & indata(31) & indata(23) & indata(15) & indata(7) &
|
indata(63) & indata(55) & indata(47) & indata(39) & indata(31) & indata(23) & indata(15) & indata(7) &
|
indata(56) & indata(48) & indata(40) & indata(32) & indata(24) & indata(16) & indata(8) & indata(0) &
|
indata(56) & indata(48) & indata(40) & indata(32) & indata(24) & indata(16) & indata(8) & indata(0) &
|
| Line 518... |
Line 387... |
indata(60) & indata(52) & indata(44) & indata(36) & indata(28) & indata(20) & indata(12) & indata(4) &
|
indata(60) & indata(52) & indata(44) & indata(36) & indata(28) & indata(20) & indata(12) & indata(4) &
|
indata(62) & indata(54) & indata(46) & indata(38) & indata(30) & indata(22) & indata(14) & indata(6);
|
indata(62) & indata(54) & indata(46) & indata(38) & indata(30) & indata(22) & indata(14) & indata(6);
|
rdy <= '0'; -- Manage the "Data ready" signal
|
rdy <= '0'; -- Manage the "Data ready" signal
|
end if;
|
end if;
|
if ready = '0' then --ready is really a "crypto in progress" signal
|
if ready = '0' then --ready is really a "crypto in progress" signal
|
|
-- Copy previous round output message data into local wire
|
C17(1 to 32) := outmsg(32 to 63);
|
C17(1 to 32) := outmsg(32 to 63);
|
C17(33 to 64) := outmsg(0 to 31);
|
C17(33 to 64) := outmsg(0 to 31);
|
|
|
|
-- clock output message data to output vector. C17 was not strictly required but it made things easier for me.
|
outdata <= C17(40) & C17(8) & C17(48) & C17(16) & C17(56) & C17(24) & C17(64) & C17(32) &
|
outdata <= C17(40) & C17(8) & C17(48) & C17(16) & C17(56) & C17(24) & C17(64) & C17(32) &
|
C17(39) & C17(7) & C17(47) & C17(15) & C17(55) & C17(23) & C17(63) & C17(31) &
|
C17(39) & C17(7) & C17(47) & C17(15) & C17(55) & C17(23) & C17(63) & C17(31) &
|
C17(38) & C17(6) & C17(46) & C17(14) & C17(54) & C17(22) & C17(62) & C17(30) &
|
C17(38) & C17(6) & C17(46) & C17(14) & C17(54) & C17(22) & C17(62) & C17(30) &
|
C17(37) & C17(5) & C17(45) & C17(13) & C17(53) & C17(21) & C17(61) & C17(29) &
|
C17(37) & C17(5) & C17(45) & C17(13) & C17(53) & C17(21) & C17(61) & C17(29) &
|
C17(36) & C17(4) & C17(44) & C17(12) & C17(52) & C17(20) & C17(60) & C17(28) &
|
C17(36) & C17(4) & C17(44) & C17(12) & C17(52) & C17(20) & C17(60) & C17(28) &
|
C17(35) & C17(3) & C17(43) & C17(11) & C17(51) & C17(19) & C17(59) & C17(27) &
|
C17(35) & C17(3) & C17(43) & C17(11) & C17(51) & C17(19) & C17(59) & C17(27) &
|
C17(34) & C17(2) & C17(42) & C17(10) & C17(50) & C17(18) & C17(58) & C17(26) &
|
C17(34) & C17(2) & C17(42) & C17(10) & C17(50) & C17(18) & C17(58) & C17(26) &
|
C17(33) & C17(1) & C17(41) & C17(9) & C17(49) & C17(17) & C17(57) & C17(25);
|
C17(33) & C17(1) & C17(41) & C17(9) & C17(49) & C17(17) & C17(57) & C17(25);
|
rdy <= '1';
|
rdy <= '1'; -- indicate that valid output is on the bus
|
end if;
|
end if;
|
when others =>
|
when others =>
|
inmsg <= outmsg;
|
inmsg <= outmsg; -- clock previous round output into next round input vector
|
rdy <= '0';
|
rdy <= '0'; -- manage the "data ready" signal
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
end process setdata;
|
end process setdata;
|
|
|
|
|
-- This handles the READY signal and counts the counters
|
-- *************************************************************
|
|
-- * This handles the READY signal and counts the counters
|
|
-- *************************************************************
|
Control: process (clk, ready, ds, RST, countup)
|
Control: process (clk, ready, ds, RST, countup)
|
|
|
begin
|
begin
|
|
|
if RST = '1' then
|
if RST = '1' then
|
|
-- assign reset values
|
ready <= '1';
|
ready <= '1';
|
countup <= 0;
|
countup <= 0;
|
|
rdy_next_cycle <= '0';
|
|
rdy_next_next_cycle <= '0';
|
|
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
|
rdy_next_cycle <= '0';
|
|
rdy_next_next_cycle <= '0';
|
if ready = '1' then
|
if ready = '1' then
|
if ds = '1' then
|
if ds = '1' then
|
|
-- data is being accepted. Assign starting clock and Data Ready values
|
ready <= '0';
|
ready <= '0';
|
countup <= 1;
|
countup <= 1;
|
end if;
|
end if;
|
else
|
else
|
if countup = 0 then
|
if countup = 0 then
|
|
-- if counter is cleared and no input data, then
|
|
-- indicate that device is waiting for work
|
if ds = '0' then
|
if ds = '0' then
|
ready <= '1';
|
ready <= '1';
|
end if;
|
end if;
|
|
elsif countup < 14 then
|
|
-- for counter = 1-13, just increment the counter
|
|
countup <= countup + 1;
|
elsif countup < 15 then
|
elsif countup < 15 then
|
|
-- for counter = 14, increment the counter and
|
|
-- indicate that data will be ready in two clocks
|
countup <= countup + 1;
|
countup <= countup + 1;
|
|
rdy_next_next_cycle <= '1';
|
else
|
else
|
|
-- for counter = 15, increment the counter and
|
|
-- indicate that data will be ready on the next clock
|
countup <= 0;
|
countup <= 0;
|
|
rdy_next_cycle <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end process control;
|
end process control;
|
| Line 1135... |
Line 1025... |
-- the first 32 bits of the round output are the last 32 bits of the round input.
|
-- the first 32 bits of the round output are the last 32 bits of the round input.
|
outmsg(0 to 31) <= inmsg(32 to 63);
|
outmsg(0 to 31) <= inmsg(32 to 63);
|
|
|
end des;
|
end des;
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
