| Line 52... |
Line 52... |
);
|
);
|
end v_riscmcu;
|
end v_riscmcu;
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|
|
architecture riscmcu of v_riscmcu is
|
architecture riscmcu of v_riscmcu is
|
|
|
signal extpin : std_logic;
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signal ext_irq_pin, ext_timer_clk_pin : std_logic;
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|
|
signal clk, clrn, div2, div4, div8, div16 : std_logic;
|
signal clk, clrn, div2, div4, div8, div16 : std_logic;
|
signal sr, reg_rd, reg_rr, c, addrbus: std_logic_vector(7 downto 0);
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signal sr, reg_rd, reg_rr, c, addrbus: std_logic_vector(7 downto 0);
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|
|
signal pc, offset : std_logic_vector(8 downto 0);
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signal pc, offset : std_logic_vector(8 downto 0);
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| Line 95... |
Line 95... |
signal set : std_logic;
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signal set : std_logic;
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|
|
signal asel : integer range 0 to 1;
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signal asel : integer range 0 to 1;
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signal bsel : integer range 0 to 3;
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signal bsel : integer range 0 to 3;
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|
|
|
-- Frequency Divider - Divide clock by 2(div2), 4(div4), 8(div8) and 16(div16)
|
component v_freqdiv
|
component v_freqdiv
|
port ( clock : in std_logic;
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port ( clock : in std_logic;
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div2, div4, div8, div16 : buffer std_logic
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div2, div4, div8, div16 : buffer std_logic
|
);
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);
|
end component;
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end component;
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|
|
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-- Program Counter (9 bit wide)
|
component v_pc
|
component v_pc
|
port ( offset : in std_logic_vector(8 downto 0);
|
port ( offset : in std_logic_vector(8 downto 0);
|
en, addoffset, push, pull, vec2, vec4 : in std_logic;
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en, addoffset, push, pull, vec2, vec4 : in std_logic;
|
clk, clrn : in std_logic;
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clk, clrn : in std_logic;
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pc : buffer std_logic_vector(8 downto 0)
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pc : buffer std_logic_vector(8 downto 0)
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);
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);
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end component;
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end component;
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|
|
|
-- Program ROM (512 words)
|
component v_rom
|
component v_rom
|
port ( pc : in std_logic_vector(8 downto 0);
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port ( pc : in std_logic_vector(8 downto 0);
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instruction : out std_logic_vector(15 downto 0)
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instruction : out std_logic_vector(15 downto 0)
|
);
|
);
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end component;
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end component;
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|
|
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-- Instruction Register (16 bit wide)
|
component v_ir
|
component v_ir
|
port ( instruction : in std_logic_vector(15 downto 0);
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port ( instruction : in std_logic_vector(15 downto 0);
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en, clk, clrn : in std_logic;
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en, clk, clrn : in std_logic;
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ir : buffer std_logic_vector(15 downto 0);
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ir : buffer std_logic_vector(15 downto 0);
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imm_value : out std_logic_vector(7 downto 0);
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imm_value : out std_logic_vector(7 downto 0);
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rd, rr : out integer range 0 to 15
|
rd, rr : out integer range 0 to 15
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Control Unit (with IO address decoder module inside)
|
component v_controlunit
|
component v_controlunit
|
port ( ir : in std_logic_vector(15 downto 0);
|
port ( ir : in std_logic_vector(15 downto 0);
|
sr : in std_logic_vector(7 downto 0);
|
sr : in std_logic_vector(7 downto 0);
|
clk, clrn : in std_logic;
|
clk, clrn : in std_logic;
|
skip, extirq, timerirq : in std_logic;
|
skip, extirq, timerirq : in std_logic;
|
| Line 175... |
Line 180... |
rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic;
|
rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic;
|
rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic
|
rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- General Purpose Register (16 x 8bit)
|
component v_gpr
|
component v_gpr
|
port ( c : in std_logic_vector(7 downto 0);
|
port ( c : in std_logic_vector(7 downto 0);
|
wr_reg, inc_zp, dec_zp : in std_logic;
|
wr_reg, inc_zp, dec_zp : in std_logic;
|
rd, rr, dest : in integer range 0 to 15;
|
rd, rr, dest : in integer range 0 to 15;
|
clk, clrn : in std_logic;
|
clk, clrn : in std_logic;
|
reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0)
|
reg_rd, reg_rr, addrbus : out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- ALU
|
component v_alu
|
component v_alu
|
port ( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
|
port ( reg_rd, reg_rr, imm_value : in std_logic_vector(7 downto 0);
|
c2a, c2b : in std_logic;
|
c2a, c2b : in std_logic;
|
asel : in integer range 0 to 1;
|
asel : in integer range 0 to 1;
|
bsel : in integer range 0 to 3;
|
bsel : in integer range 0 to 3;
|
| Line 210... |
Line 217... |
tosr : buffer std_logic_vector (6 downto 0);
|
tosr : buffer std_logic_vector (6 downto 0);
|
skip : out std_logic
|
skip : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Status Register (8 bit wide, flags are ITHSVNZC)
|
component v_sr
|
component v_sr
|
port ( clk,clrn: in std_logic;
|
port ( clk,clrn: in std_logic;
|
sren,tosr : in std_logic_vector(6 downto 0);
|
sren,tosr : in std_logic_vector(6 downto 0);
|
srsel : in integer range 0 to 7;
|
srsel : in integer range 0 to 7;
|
clr_i,set_i,bset,bclr : in std_logic;
|
clr_i,set_i,bset,bclr : in std_logic;
|
| Line 221... |
Line 229... |
c : inout std_logic_vector(7 downto 0);
|
c : inout std_logic_vector(7 downto 0);
|
sr : inout std_logic_vector(7 downto 0)
|
sr : inout std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Data RAM (128 bytes)
|
component v_ram
|
component v_ram
|
port ( addrbus : in std_logic_vector(7 downto 0);
|
port ( addrbus : in std_logic_vector(7 downto 0);
|
rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic;
|
rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic;
|
clk, clrn : in std_logic;
|
clk, clrn : in std_logic;
|
c : inout std_logic_vector(7 downto 0)
|
c : inout std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- Standard 8-bit I/O Port module (all ports share this same module)
|
component v_port
|
component v_port
|
port ( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic;
|
port ( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic;
|
clk, clrn : in std_logic;
|
clk, clrn : in std_logic;
|
c : inout std_logic_vector(7 downto 0);
|
c : inout std_logic_vector(7 downto 0);
|
pin : inout std_logic_vector(7 downto 0)
|
pin : inout std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- 8-bit Timer with overflow interrupt request, can drive by external clock source
|
component v_timer
|
component v_timer
|
port ( extpin, clr_tov0 : in std_logic;
|
port ( extpin, clr_tov0 : in std_logic;
|
rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic;
|
rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic;
|
rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic;
|
rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic;
|
clk, clrn : in std_logic;
|
clk, clrn : in std_logic;
|
c : inout std_logic_vector(7 downto 0);
|
c : inout std_logic_vector(7 downto 0);
|
timerirq : out std_logic
|
timerirq : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
-- External Interrupt
|
component v_extint
|
component v_extint
|
port ( clk, clrn, extpin, clr_intf : in std_logic;
|
port ( clk, clrn, extpin, clr_intf : in std_logic;
|
rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic;
|
rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic;
|
extirq : out std_logic;
|
extirq : out std_logic;
|
c : inout std_logic_vector(7 downto 0)
|
c : inout std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
|
--U_v_freqdiv: v_freqdiv
|
U_v_freqdiv: v_freqdiv
|
-- port map (clock, div2, div4, div8, div16);
|
port map (clock, div2, div4, div8, div16);
|
|
|
|
U_v_pc: v_pc
|
U_v_pc: v_pc
|
port map (offset, en, addoffset, push, pull, vec2, vec4, clk, clrn, pc);
|
port map (offset, en, addoffset, push, pull, vec2, vec4, clk, clrn, pc);
|
|
|
U_v_rom: v_rom
|
U_v_rom: v_rom
|
| Line 285... |
Line 296... |
|
|
U_v_ram: v_ram
|
U_v_ram: v_ram
|
port map (addrbus, rd_ram, wr_ram, ld_mar, ld_mbr, clk, clrn, c);
|
port map (addrbus, rd_ram, wr_ram, ld_mar, ld_mbr, clk, clrn, c);
|
|
|
U_v_timer: v_timer
|
U_v_timer: v_timer
|
port map (extpin, clr_tov0, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, clk, clrn, c, timerirq);
|
port map (ext_timer_clk_pin, clr_tov0, rd_timsk, wr_timsk, rd_tifr, wr_tifr, rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0, clk, clrn, c, timerirq);
|
|
|
U_v_extint: v_extint
|
U_v_extint: v_extint
|
port map (clk, clrn, extpin, clr_intf, rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk, extirq, c);
|
port map (clk, clrn, ext_irq_pin, clr_intf, rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk, extirq, c);
|
|
|
|
|
|
-- The same module v_port is used by 3 I/O ports, just the signals are different
|
U_v_portB: v_port
|
U_v_portB: v_port
|
port map (rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, clk, clrn, c, pinb);
|
port map (rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb, clk, clrn, c, pinb);
|
|
|
U_v_portC: v_port
|
U_v_portC: v_port
|
port map (rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, clk, clrn, c, pinc);
|
port map (rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc, clk, clrn, c, pinc);
|
|
|
U_v_portD: v_port
|
U_v_portD: v_port
|
port map (rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind, clk, clrn, c, pind);
|
port map (rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind, clk, clrn, c, pind);
|
|
|
extpin <= pind(7);
|
-- Global reset, it resets ALL flip-flops and registers to the initial state (normally gnd)
|
clrn <= reset;
|
clrn <= reset;
|
clk <= div4;
|
|
vcc <= '1';
|
vcc <= '1';
|
gnd <= '0';
|
gnd <= '0';
|
t_flag <= sr(6);
|
t_flag <= sr(6);
|
c_flag <= sr(0);
|
c_flag <= sr(0);
|
|
|
|
-- These are the external interrupt request pin and external timer clock source pin
|
|
-- They share pins with the I/O ports
|
|
-- TIPS: You can use any of the 24 I/O pins, I use pind(7) for my applications
|
|
ext_irq_pin <= pind(2);
|
|
ext_timer_clk_pin <= pind(4);
|
|
|
|
-- When I use the UP1 board, the on-board 25 MHz clock is too fast and
|
|
-- I need to divide it by 4 so that the MCU can run
|
|
-- For waveform simulation, it does not require division (clk <= clock)
|
|
-- TIPS: To have division, uncomment v_freqdiv module instantation on top of the page and
|
|
-- assign clk with div2, div4, div8 or div16
|
|
clk <= clock;
|
|
|
|
|
end riscmcu;
|
end riscmcu;
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
