| Line 163... |
Line 163... |
cf_rst_n : out std_logic;
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cf_rst_n : out std_logic;
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cf_cs0_n : out std_logic;
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cf_cs0_n : out std_logic;
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cf_cs1_n : out std_logic;
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cf_cs1_n : out std_logic;
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cf_rd_n : out std_logic;
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cf_rd_n : out std_logic;
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cf_wr_n : out std_logic;
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cf_wr_n : out std_logic;
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cf_cs16_n : out std_logic;
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cf_a : out std_logic_vector(2 downto 0);
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cf_a : out std_logic_vector(2 downto 0);
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cf_d : inout std_logic_vector(15 downto 0);
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cf_d : inout std_logic_vector(15 downto 0);
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-- cf_d : inout std_logic_vector(7 downto 0);
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-- Parallel I/O port
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-- Parallel I/O port
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porta : inout std_logic_vector(7 downto 0);
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porta : inout std_logic_vector(7 downto 0);
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portb : inout std_logic_vector(7 downto 0);
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portb : inout std_logic_vector(7 downto 0);
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| Line 980... |
Line 978... |
cf_cs, cf_rd, cf_wr, cf_d )
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cf_cs, cf_rd, cf_wr, cf_d )
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begin
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begin
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cf_rst_n <= Reset_n;
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cf_rst_n <= Reset_n;
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cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
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cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
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cf_cs1_n <= not( cf_cs and cpu_addr(3));
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cf_cs1_n <= not( cf_cs and cpu_addr(3));
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cf_cs16_n <= '1';
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cf_wr <= cf_cs and (not cpu_rw);
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cf_wr <= cf_cs and (not cpu_rw);
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cf_rd <= cf_cs and cpu_rw;
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cf_rd <= cf_cs and cpu_rw;
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cf_wr_n <= not cf_wr;
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cf_wr_n <= not cf_wr;
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cf_rd_n <= not cf_rd;
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cf_rd_n <= not cf_rd;
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cf_a <= cpu_addr(2 downto 0);
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cf_a <= cpu_addr(2 downto 0);
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if cf_wr = '1' then
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if cf_wr = '1' then
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cf_d(7 downto 0) <= cpu_data_out;
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cf_d(7 downto 0) <= cpu_data_out;
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cf_d(15 downto 8) <= (others => '0');
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else
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else
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cf_d(7 downto 0) <= "ZZZZZZZZ";
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cf_d(7 downto 0) <= (others => 'Z');
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cf_d(15 downto 8) <= (others => 'Z');
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end if;
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end if;
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cf_data_out <= cf_d(7 downto 0);
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cf_data_out <= cf_d(7 downto 0);
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cf_d(15 downto 8) <= "ZZZZZZZZ";
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end process;
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end process;
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--
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--
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-- Hold CF access for a few cycles
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-- Hold CF access for a few cycles
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--
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--
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