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[/] [System09/] [rev_86/] [rtl/] [System09_Digilent_3S200/] [System09_Digilent_3S200.ucf] - Diff between revs 19 and 22

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Rev 19 Rev 22
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#PACE: Start of Constraints generated by PACE
#PACE: Start of Constraints generated by PACE
 
 
#PACE: Start of PACE I/O Pin Assignments
#PACE: Start of PACE I/O Pin Assignments
NET "SysClk"        LOC = "T9"  ;
NET "sys_clk"        LOC = "T9"  ;
#
#
# PUSH BUTTONS
# PUSH BUTTONS
#
#
NET "Reset_sw"      LOC = "L14"  ;
NET "rst_sw"        LOC = "L14"  ;
NET "nmi_sw"        LOC = "L13"  ;
NET "nmi_sw"        LOC = "L13"  ;
#
#
# LEDs
# LEDs
#
#
NET "leds<0>"       LOC = "K12";
NET "leds<0>"       LOC = "K12";
Line 128... Line 128...
NET "ram2_data<12>"  LOC = "C3"  ;
NET "ram2_data<12>"  LOC = "C3"  ;
NET "ram2_data<13>"  LOC = "K2"  ;
NET "ram2_data<13>"  LOC = "K2"  ;
NET "ram2_data<14>"  LOC = "M1"  ;
NET "ram2_data<14>"  LOC = "M1"  ;
NET "ram2_data<15>"  LOC = "N1"  ;
NET "ram2_data<15>"  LOC = "N1"  ;
#
#
# Timing Groups
 
#
 
INST "ram_oen"      TNM = "gram_rw";
 
INST "ram_wen"      TNM = "gram_rw";
 
INST "ram_addr<0>"  TNM = "gram_addr";
 
INST "ram_addr<1>"  TNM = "gram_addr";
 
INST "ram_addr<2>"  TNM = "gram_addr";
 
INST "ram_addr<3>"  TNM = "gram_addr";
 
INST "ram_addr<4>"  TNM = "gram_addr";
 
INST "ram_addr<5>"  TNM = "gram_addr";
 
INST "ram_addr<6>"  TNM = "gram_addr";
 
INST "ram_addr<7>"  TNM = "gram_addr";
 
INST "ram_addr<8>"  TNM = "gram_addr";
 
INST "ram_addr<9>"  TNM = "gram_addr";
 
INST "ram_addr<10>" TNM = "gram_addr";
 
INST "ram_addr<11>" TNM = "gram_addr";
 
INST "ram_addr<12>" TNM = "gram_addr";
 
INST "ram_addr<13>" TNM = "gram_addr";
 
INST "ram_addr<14>" TNM = "gram_addr";
 
INST "ram_addr<15>" TNM = "gram_addr";
 
INST "ram_addr<16>" TNM = "gram_addr";
 
INST "ram_addr<17>" TNM = "gram_addr";
 
#
 
INST "ram1_cen"      TNM = "gram_cs";
 
INST "ram1_lbn"      TNM = "gram_ds";
 
INST "ram1_ubn"      TNM = "gram_ds";
 
INST "ram1_data<0>"  TNM = "gram_data";
 
INST "ram1_data<1>"  TNM = "gram_data";
 
INST "ram1_data<2>"  TNM = "gram_data";
 
INST "ram1_data<3>"  TNM = "gram_data";
 
INST "ram1_data<4>"  TNM = "gram_data";
 
INST "ram1_data<5>"  TNM = "gram_data";
 
INST "ram1_data<6>"  TNM = "gram_data";
 
INST "ram1_data<7>"  TNM = "gram_data";
 
INST "ram1_data<8>"  TNM = "gram_data";
 
INST "ram1_data<9>"  TNM = "gram_data";
 
INST "ram1_data<10>" TNM = "gram_data";
 
INST "ram1_data<11>" TNM = "gram_data";
 
INST "ram1_data<12>" TNM = "gram_data";
 
INST "ram1_data<13>" TNM = "gram_data";
 
INST "ram1_data<14>" TNM = "gram_data";
 
INST "ram1_data<15>" TNM = "gram_data";
 
#
 
INST "ram2_cen"      TNM = "gram_cs";
 
INST "ram2_lbn"      TNM = "gram_ds";
 
INST "ram2_ubn"      TNM = "gram_ds";
 
INST "ram2_data<0>"  TNM = "gram_data";
 
INST "ram2_data<1>"  TNM = "gram_data";
 
INST "ram2_data<2>"  TNM = "gram_data";
 
INST "ram2_data<3>"  TNM = "gram_data";
 
INST "ram2_data<4>"  TNM = "gram_data";
 
INST "ram2_data<5>"  TNM = "gram_data";
 
INST "ram2_data<6>"  TNM = "gram_data";
 
INST "ram2_data<7>"  TNM = "gram_data";
 
INST "ram2_data<8>"  TNM = "gram_data";
 
INST "ram2_data<9>"  TNM = "gram_data";
 
INST "ram2_data<10>" TNM = "gram_data";
 
INST "ram2_data<11>" TNM = "gram_data";
 
INST "ram2_data<12>" TNM = "gram_data";
 
INST "ram2_data<13>" TNM = "gram_data";
 
INST "ram2_data<14>" TNM = "gram_data";
 
INST "ram2_data<15>" TNM = "gram_data";
 
#
 
# Timing Constraints
# Timing Constraints
#
#
NET "sysclk" TNM_NET = "sysclk";
NET "sys_clk" TNM_NET = "sys_clk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 20 ns LOW 50 %;
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 20 ns LOW 50 %;
TIMEGRP "gram_cs"   OFFSET = OUT 20 ns AFTER "sysclk";
 
TIMEGRP "gram_ds"   OFFSET = OUT 20 ns AFTER "sysclk";
 
TIMEGRP "gram_rw"   OFFSET = OUT 20 ns AFTER "sysclk";
 
TIMEGRP "gram_addr" OFFSET = OUT 20 ns AFTER "sysclk";
 
TIMEGRP "gram_data" OFFSET = OUT 20 ns AFTER "sysclk";
 
TIMEGRP "gram_data" OFFSET = IN  10 ns BEFORE "sysclk";
 
 
 
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Area Constraints
 
 
#PACE: Start of PACE Prohibit Constraints
#PACE: Start of PACE Prohibit Constraints
 
 

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