| Line 47... |
Line 47... |
--
|
--
|
-- Version 0.6 - 5 September 2003
|
-- Version 0.6 - 5 September 2003
|
-- Runs SBUG
|
-- Runs SBUG
|
--
|
--
|
-- Version 1.0- 6 Sep 2003 - John Kent
|
-- Version 1.0- 6 Sep 2003 - John Kent
|
-- Inverted SysClk
|
-- Inverted sys_clk
|
-- Initial release to Open Cores
|
-- Initial release to Open Cores
|
--
|
--
|
-- Version 1.1 - 17 Jan 2004 - John Kent
|
-- Version 1.1 - 17 Jan 2004 - John Kent
|
-- Updated miniUart.
|
-- Updated miniUart.
|
--
|
--
|
| Line 82... |
Line 82... |
-- Increased CPU clock from 12.5MHz to 25 MHz.
|
-- Increased CPU clock from 12.5MHz to 25 MHz.
|
-- Removed some of the global clock buffers
|
-- Removed some of the global clock buffers
|
-- Added LED output register
|
-- Added LED output register
|
-- Changed address decoding to 4K Blocks
|
-- Changed address decoding to 4K Blocks
|
--
|
--
|
-- Vesrion 2.3 - 1 June 2007 - John Kent
|
-- Version 2.3 - 1 June 2007 - John Kent
|
-- Updated VDU & ACIA
|
-- Updated VDU & ACIA
|
-- Changed decoding for Sys09Bug
|
-- Changed decoding for Sys09Bug
|
--
|
--
|
|
-- Version 2.4 - 31 January 2008 - John Kent
|
|
-- ACIA does not appear to work.
|
|
-- Made RAM OE and WE strobes synchonous to sys_clk
|
|
--
|
--===========================================================================--
|
--===========================================================================--
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
entity My_System09 is
|
entity My_System09 is
|
port(
|
port(
|
SysClk : in Std_Logic; -- System Clock input
|
sys_clk : in Std_Logic; -- System Clock input
|
Reset_sw : in Std_logic; -- Master Reset input (active low)
|
rst_sw : in Std_logic; -- Master Reset input (active high)
|
nmi_sw : in Std_logic;
|
nmi_sw : in Std_logic;
|
|
|
-- Memory Interface signals
|
-- Memory Interface signals
|
ram_addr : out Std_Logic_Vector(17 downto 0);
|
ram_addr : out Std_Logic_Vector(17 downto 0);
|
ram_wen : out Std_Logic;
|
ram_wen : out Std_Logic;
|
| Line 118... |
Line 122... |
|
|
-- PS/2 Keyboard
|
-- PS/2 Keyboard
|
ps2c : inout Std_logic;
|
ps2c : inout Std_logic;
|
ps2d : inout Std_Logic;
|
ps2d : inout Std_Logic;
|
|
|
-- Uart Interface
|
-- ACIA Interface
|
rxd : in Std_Logic;
|
rxd : in Std_Logic;
|
txd : out Std_Logic;
|
txd : out Std_Logic;
|
|
|
-- CRTC output signals
|
-- CRTC output signals
|
vs : out Std_Logic;
|
vs : out Std_Logic;
|
| Line 165... |
Line 169... |
|
|
-- FLEX9 RAM
|
-- FLEX9 RAM
|
signal flex_cs : Std_logic;
|
signal flex_cs : Std_logic;
|
signal flex_data_out : Std_Logic_Vector(7 downto 0);
|
signal flex_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
-- UART Interface signals
|
-- ACIA Interface signals
|
signal acia_clk : std_logic;
|
signal acia_clk : std_logic;
|
signal acia_data_out : Std_Logic_Vector(7 downto 0);
|
signal acia_data_out : Std_Logic_Vector(7 downto 0);
|
signal acia_cs : Std_Logic;
|
signal acia_cs : Std_Logic;
|
signal acia_irq : Std_Logic;
|
signal acia_irq : Std_Logic;
|
signal DCD_n : Std_Logic;
|
signal acia_rxd : Std_Logic;
|
signal RTS_n : Std_Logic;
|
signal acia_txd : Std_Logic;
|
signal CTS_n : Std_Logic;
|
signal acia_dcd_n : Std_Logic;
|
|
-- signal acia_rts_n : Std_Logic;
|
|
signal acia_cts_n : Std_Logic;
|
|
|
-- keyboard port
|
-- keyboard port
|
signal keyboard_data_out : std_logic_vector(7 downto 0);
|
signal keyboard_data_out : std_logic_vector(7 downto 0);
|
signal keyboard_cs : std_logic;
|
signal keyboard_cs : std_logic;
|
signal keyboard_irq : std_logic;
|
signal keyboard_irq : std_logic;
|
| Line 304... |
Line 310... |
);
|
);
|
end component;
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- Open Cores Mini UART
|
-- 6850 ACIA
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_6850
|
component ACIA_6850
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock
|
clk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic; -- miniUART Chip Select
|
cs : in Std_Logic; -- ACIA Chip Select
|
rw : in Std_Logic; -- Read / Not Write
|
rw : in Std_Logic; -- Read / Not Write
|
irq : out Std_Logic; -- Interrupt
|
irq : out Std_Logic; -- Interrupt
|
Addr : in Std_Logic; -- Register Select
|
Addr : in Std_Logic; -- Register Select
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
| Line 499... |
Line 505... |
Addr => cpu_addr(0),
|
Addr => cpu_addr(0),
|
Datain => cpu_data_out,
|
Datain => cpu_data_out,
|
DataOut => acia_data_out,
|
DataOut => acia_data_out,
|
RxC => acia_clk,
|
RxC => acia_clk,
|
TxC => acia_clk,
|
TxC => acia_clk,
|
RxD => rxd,
|
RxD => acia_rxd,
|
TxD => txd,
|
TxD => acia_txd,
|
DCD_n => dcd_n,
|
DCD_n => acia_dcd_n,
|
CTS_n => cts_n,
|
CTS_n => acia_cts_n,
|
RTS_n => rts_n
|
RTS_n => open
|
);
|
);
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
| Line 518... |
Line 524... |
generic map(
|
generic map(
|
SYS_Clock_Frequency => SYS_Clock_Frequency,
|
SYS_Clock_Frequency => SYS_Clock_Frequency,
|
ACIA_Clock_Frequency => ACIA_Clock_Frequency
|
ACIA_Clock_Frequency => ACIA_Clock_Frequency
|
)
|
)
|
port map(
|
port map(
|
clk => SysClk,
|
clk => sys_clk,
|
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
| Line 621... |
Line 627... |
-- Clock divider
|
-- Clock divider
|
-- Assumes 50 MHz system clock
|
-- Assumes 50 MHz system clock
|
-- 25MHz pixel clock
|
-- 25MHz pixel clock
|
-- 25MHz CPU clock
|
-- 25MHz CPU clock
|
--
|
--
|
sys09_clock : process( SysClk, clk_count )
|
sys09_clock : process( sys_clk, clk_count )
|
begin
|
begin
|
if SysClk'event and SysClk='0' then
|
if sys_clk'event and sys_clk='1' then
|
clk_count <= not clk_count;
|
clk_count <= not clk_count;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
mem_decode: process( cpu_clk, Reset_sw,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
cpu_addr, cpu_rw, cpu_vma,
|
|
dat_cs, dat_addr,
|
dat_cs, dat_addr,
|
rom_data_out,
|
rom_data_out,
|
acia_data_out,
|
acia_data_out,
|
keyboard_data_out,
|
keyboard_data_out,
|
vdu_data_out,
|
vdu_data_out,
|
| Line 647... |
Line 652... |
leds_data_out,
|
leds_data_out,
|
flex_data_out,
|
flex_data_out,
|
ram_data_out
|
ram_data_out
|
)
|
)
|
begin
|
begin
|
if cpu_addr( 15 downto 8 ) = "11111111" then
|
cpu_data_in <= (others=>'0');
|
cpu_data_in <= rom_data_out;
|
dat_cs <= '0';
|
dat_cs <= cpu_vma; -- write DAT
|
rom_cs <= '0';
|
rom_cs <= cpu_vma; -- read ROM
|
|
acia_cs <= '0';
|
acia_cs <= '0';
|
keyboard_cs <= '0';
|
keyboard_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
seg_cs <= '0';
|
seg_cs <= '0';
|
leds_cs <= '0';
|
leds_cs <= '0';
|
flex_cs <= '0';
|
flex_cs <= '0';
|
ram_cs <= '0';
|
ram_cs <= '0';
|
else
|
-- timer_cs <= '0';
|
case dat_addr(3 downto 0) is
|
-- trap_cs <= '0';
|
|
-- pb_cs <= '0';
|
|
-- ide_cs <= '0';
|
|
-- ether_cs <= '0';
|
|
-- slot1_cs <= '0';
|
|
-- slot2_cs <= '0';
|
|
|
|
if cpu_addr( 15 downto 8 ) = "11111111" then
|
|
cpu_data_in <= rom_data_out;
|
|
dat_cs <= cpu_vma; -- write DAT
|
|
rom_cs <= cpu_vma; -- read ROM
|
|
--
|
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
|
--
|
|
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
|
--
|
--
|
-- Monitor ROM $F000 - $FFFF
|
-- Monitor ROM $F000 - $FFFF
|
--
|
--
|
when "1111" => -- $XF000 - $XFFFF
|
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
dat_cs <= '0'; -- write DAT
|
|
rom_cs <= cpu_vma; -- read ROM
|
rom_cs <= cpu_vma; -- read ROM
|
acia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
seg_cs <= '0';
|
|
leds_cs <= '0';
|
|
flex_cs <= '0';
|
|
ram_cs <= '0';
|
|
|
|
--
|
--
|
-- IO Devices $E000 - $EFFF
|
-- IO Devices $E000 - $EFFF
|
--
|
--
|
when "1110" => -- $XE000 - $XEFFF
|
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
|
dat_cs <= '0';
|
case cpu_addr(11 downto 8) is
|
rom_cs <= '0';
|
--
|
|
-- SWTPC peripherals from $E000 to $E0FF
|
|
--
|
|
when "0000" =>
|
case cpu_addr(7 downto 4) is
|
case cpu_addr(7 downto 4) is
|
--
|
--
|
-- UART / ACIA ($E000 - $E00F)
|
-- ACIA ($E000 - $E00F)
|
--
|
--
|
when "0000" =>
|
when "0000" =>
|
cpu_data_in <= acia_data_out;
|
cpu_data_in <= acia_data_out;
|
acia_cs <= cpu_vma;
|
acia_cs <= cpu_vma;
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
seg_cs <= '0';
|
|
leds_cs <= '0';
|
|
|
|
--
|
--
|
-- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
|
-- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC)
|
--
|
--
|
|
|
--
|
--
|
-- Keyboard port ($E020 - $E02F)
|
-- Keyboard port ($E020 - $E02F)
|
--
|
--
|
when "0010" =>
|
when "0010" =>
|
cpu_data_in <= keyboard_data_out;
|
cpu_data_in <= keyboard_data_out;
|
acia_cs <= '0';
|
|
keyboard_cs <= cpu_vma;
|
keyboard_cs <= cpu_vma;
|
vdu_cs <= '0';
|
|
seg_cs <= '0';
|
|
leds_cs <= '0';
|
|
|
|
--
|
--
|
-- VDU port ($E030 - $E03F)
|
-- VDU port ($E030 - $E03F)
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
cpu_data_in <= vdu_data_out;
|
cpu_data_in <= vdu_data_out;
|
acia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= cpu_vma;
|
vdu_cs <= cpu_vma;
|
seg_cs <= '0';
|
|
leds_cs <= '0';
|
|
|
|
--
|
--
|
-- Reserved - Compact Flash ($E040 - $E04F) (B5-X300)
|
-- Reserved - SWTPc MP-T ($E040 - $E04F)
|
--
|
--
|
|
|
--
|
--
|
-- Reserved - Timer ($E050 - $E05F) (B5-X300)
|
-- Reserved - Timer ($E050 - $E05F) (B5-X300)
|
--
|
--
|
| Line 749... |
Line 749... |
-- Read Switched port ($E0A0 - $E0AF)
|
-- Read Switched port ($E0A0 - $E0AF)
|
-- Write LEDS
|
-- Write LEDS
|
--
|
--
|
when "1010" =>
|
when "1010" =>
|
cpu_data_in <= leds_data_out;
|
cpu_data_in <= leds_data_out;
|
acia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
seg_cs <= '0';
|
|
leds_cs <= cpu_vma;
|
leds_cs <= cpu_vma;
|
|
|
--
|
--
|
-- 7 segment display port ($E0B0 - $E0BF)
|
-- 7 segment display port ($E0B0 - $E0BF)
|
--
|
--
|
when "1011" =>
|
when "1011" =>
|
cpu_data_in <= seg_data_out;
|
cpu_data_in <= seg_data_out;
|
acia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
seg_cs <= cpu_vma;
|
seg_cs <= cpu_vma;
|
leds_cs <= '0';
|
|
|
|
|
|
when others => -- $EXC0 to $EXFF
|
when others => -- $EXC0 to $EXFF
|
cpu_data_in <= "00000000";
|
null;
|
acia_cs <= '0';
|
end case;
|
keyboard_cs <= '0';
|
--
|
vdu_cs <= '0';
|
-- XST-3.0 Peripheral Bus goes here
|
seg_cs <= '0';
|
-- $E100 to $E1FF
|
leds_cs <= '0';
|
-- Four devices
|
|
-- IDE, Ethernet, Slot1, Slot2
|
|
--
|
|
-- when "0001" =>
|
|
-- cpu_data_in <= pb_data_out;
|
|
-- pb_cs <= cpu_vma;
|
|
-- case cpu_addr(7 downto 6) is
|
|
--
|
|
-- IDE Interface $E100 to $E13F
|
|
--
|
|
-- when "00" =>
|
|
-- ide_cs <= cpu_vma;
|
|
--
|
|
-- Ethernet Interface $E140 to $E17F
|
|
--
|
|
-- when "01" =>
|
|
-- ether_cs <= cpu_vma;
|
|
--
|
|
-- Slot 1 Interface $E180 to $E1BF
|
|
--
|
|
-- when "10" =>
|
|
-- slot1_cs <= cpu_vma;
|
|
--
|
|
-- Slot 2 Interface $E1C0 to $E1FF
|
|
--
|
|
-- when "11" =>
|
|
-- slot2_cs <= cpu_vma;
|
|
--
|
|
-- Nothing else
|
|
--
|
|
-- when others =>
|
|
-- null;
|
|
-- end case;
|
|
--
|
|
-- $E200 to $EFFF reserved for future use
|
|
--
|
|
when others =>
|
|
null;
|
end case;
|
end case;
|
flex_cs <= '0';
|
|
ram_cs <= '0';
|
|
--
|
--
|
-- FLEX RAM $0C000 - $0DFFF
|
-- FLEX RAM $0C000 - $0DFFF
|
--
|
--
|
when "1100" | "1101" => -- $0C000 - $0DFFF
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
if dat_addr(7 downto 4) = "0000" then
|
|
cpu_data_in <= flex_data_out;
|
cpu_data_in <= flex_data_out;
|
flex_cs <= cpu_vma;
|
flex_cs <= cpu_vma;
|
ram_cs <= '0';
|
|
else
|
|
cpu_data_in <= ram_data_out;
|
|
flex_cs <= '0';
|
|
ram_cs <= cpu_vma;
|
|
end if;
|
|
dat_cs <= '0';
|
|
rom_cs <= '0';
|
|
acia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
seg_cs <= '0';
|
|
leds_cs <= '0';
|
|
--
|
--
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
when others =>
|
else
|
cpu_data_in <= ram_data_out;
|
cpu_data_in <= ram_data_out;
|
rom_cs <= '0';
|
|
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
dat_cs <= '0';
|
|
acia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
seg_cs <= '0';
|
|
leds_cs <= '0';
|
|
flex_cs <= '0';
|
|
end case;
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
--
|
--
|
-- 1M byte SRAM Control
|
-- 1M byte SRAM Control
|
-- Processes to read and write memory based on bus signals
|
-- Processes to read and write memory based on bus signals
|
--
|
--
|
ram_process: process( cpu_clk,
|
ram_process: process( cpu_reset, sys_clk,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
dat_addr, ram_cs,
|
dat_addr, ram_cs,
|
ram1_ce, ram1_ub, ram1_lb, ram1_data,
|
ram1_ce, ram1_ub, ram1_lb, ram1_data,
|
ram2_ce, ram2_ub, ram2_lb, ram2_data,
|
ram2_ce, ram2_ub, ram2_lb, ram2_data,
|
ram_we, ram_oe )
|
ram_we, ram_oe )
|
begin
|
begin
|
ram_we <= (not cpu_rw) and cpu_clk;
|
--
|
ram_oe <= cpu_rw and cpu_clk;
|
-- ram_hold signal helps
|
|
--
|
|
if( cpu_reset = '1' ) then
|
|
ram_we <= '0';
|
|
ram_oe <= '0';
|
|
--
|
|
-- Clock Hold on rising edge
|
|
--
|
|
elsif( sys_clk'event and sys_clk='1' ) then
|
|
if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then
|
|
ram_we <= not cpu_rw;
|
|
ram_oe <= cpu_rw;
|
|
else
|
|
ram_we <= '0';
|
|
ram_oe <= '0';
|
|
end if;
|
|
end if;
|
|
|
ram_wen <= not ram_we;
|
ram_wen <= not ram_we;
|
ram_oen <= not ram_oe;
|
ram_oen <= not ram_oe;
|
|
|
ram1_ce <= ram_cs and (not cpu_addr(1));
|
ram1_ce <= ram_cs and (not cpu_addr(1));
|
ram1_ub <= not cpu_addr(0);
|
ram1_ub <= not cpu_addr(0);
|
| Line 903... |
Line 924... |
end process;
|
end process;
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( Reset_sw,
|
interrupts : process( rst_sw,
|
acia_irq,
|
acia_irq,
|
keyboard_irq,
|
keyboard_irq,
|
nmi_sw
|
nmi_sw
|
)
|
)
|
begin
|
begin
|
cpu_reset <= Reset_sw; -- CPU reset is active high
|
if sys_clk'event and sys_clk = '1' then
|
|
cpu_reset <= rst_sw; -- CPU reset is active high
|
|
end if;
|
cpu_firq <= keyboard_irq;
|
cpu_firq <= keyboard_irq;
|
cpu_nmi <= nmi_sw;
|
cpu_nmi <= nmi_sw;
|
cpu_irq <= acia_irq;
|
cpu_irq <= acia_irq;
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= '0';
|
cpu_hold <= '0';
|
|
end process;
|
|
|
DCD_n <= '0';
|
--
|
CTS_n <= '0';
|
-- ACIA pin assignments
|
|
--
|
|
acia_assignments : process( rxd, acia_txd )
|
|
begin
|
|
acia_dcd_n <= '0';
|
|
acia_cts_n <= '0';
|
|
acia_rxd <= rxd;
|
|
txd <= acia_txd;
|
end process;
|
end process;
|
|
|
|
|
end my_computer; --===================== End of architecture =======================--
|
end my_computer; --===================== End of architecture =======================--
|
|
|
