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[/] [System09/] [tags/] [pre_mkfiles_rev1_merge/] [rtl/] [Spartan3/] [sbug_rom2k_b16.vhd] - Diff between revs 19 and 20

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Line 5... Line 5... 
--
 
--
 
library IEEE;
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.STD_LOGIC_ARITH.ALL;
 
use IEEE.STD_LOGIC_ARITH.ALL;
 
library unisim;
 
library unisim;
 
        use unisim.all;
 
        use unisim.vcomponents.all;
 
 
 
 
 
entity mon_rom is
 
entity mon_rom is
 
    Port (
 
    Port (
 
       clk   : in  std_logic;
 
       clk   : in  std_logic;
 
                 rst   : in  std_logic;
 
                 rst   : in  std_logic;
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    );
 
    );
 
end mon_rom;
 
end mon_rom;
 
 
 
 
 
architecture rtl of mon_rom is
 
architecture rtl of mon_rom is
 
 
 
 
 
   component RAMB16_S9
 
 
 
    generic (
 
 
 
      INIT_00, INIT_01, INIT_02, INIT_03,
 
 
 
           INIT_04, INIT_05, INIT_06, INIT_07,
 
 
 
           INIT_08, INIT_09, INIT_0A, INIT_0B,
 
 
 
      INIT_0C, INIT_0D, INIT_0E, INIT_0F,
 
 
 
      INIT_10, INIT_11, INIT_12, INIT_13,
 
 
 
           INIT_14, INIT_15, INIT_16, INIT_17,
 
 
 
           INIT_18, INIT_19, INIT_1A, INIT_1B,
 
 
 
      INIT_1C, INIT_1D, INIT_1E, INIT_1F,
 
 
 
      INIT_20, INIT_21, INIT_22, INIT_23,
 
 
 
           INIT_24, INIT_25, INIT_26, INIT_27,
 
 
 
           INIT_28, INIT_29, INIT_2A, INIT_2B,
 
 
 
      INIT_2C, INIT_2D, INIT_2E, INIT_2F,
 
 
 
      INIT_30, INIT_31, INIT_32, INIT_33,
 
 
 
           INIT_34, INIT_35, INIT_36, INIT_37,
 
 
 
           INIT_38, INIT_39, INIT_3A, INIT_3B,
 
 
 
      INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
 
 
 
    );
 
 
 
 
 
 
 
    port (
 
 
 
      do   : out std_logic_vector(7 downto 0);
 
 
 
                dop0 : out std_logic;
 
 
 
      addr : in std_logic_vector(10 downto 0);
 
 
 
      clk  : in std_logic;
 
 
 
      di   : in std_logic_vector(7 downto 0);
 
 
 
      dip0 : in std_logic;
 
 
 
                en   : in std_logic;
 
 
 
                ssr  : in std_logic;
 
 
 
                we   : in std_logic
 
 
 
    );
 
 
 
  end component RAMB16_S9;
 
 
 
 
 
 
 
signal we : std_logic;
 
signal we : std_logic;
 
signal dp : std_logic;
 
signal dp : std_logic;
 
 
 
 
 
begin
 
begin
 
 
 
 
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    INIT_3F => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
 
    INIT_3F => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
 
    )
 
    )
 
 
 
 
 
    port map (
 
    port map (
 
          do   => rdata,
 
          do   => rdata,
 
          dop0 => dp,
 
          dop(0) => dp,
 
          addr => addr,
 
          addr => addr,
 
          clk  => clk,
 
          clk  => clk,
 
     di   => wdata,
 
     di   => wdata,
 
          dip0 => dp,
 
          dip(0) => dp,
 
          en   => cs,
 
          en   => cs,
 
          ssr  => rst,
 
          ssr  => rst,
 
          we   => we
 
          we   => we
 
        );
 
        );
 
 
 
 

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