| Line 1... |
Line 1... |
---------------------------------------------------------
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--===========================================================================--
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-- --
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-- Synthesizable PS/2 Keyboard Key map ROM For Spartan 2 --
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-- --
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--===========================================================================--
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--
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--
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-- PS2 Keycode look up table
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-- File name : keymap_rom512_b4.vhd
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-- converts 7 bit key code to ASCII
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--
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-- Address bit 7 = CAPS Lock
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-- Entity name : keymap_rom
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--
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-- Purpose : PS/2 key code look up table
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-- Converts 7 bit key code to ASCII
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-- Address bit 8 = Shift
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-- Address bit 8 = Shift
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-- Address bit 7 = CAPS Lock
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-- Address bits 6 - 0 = Key code
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-- Data bits 6 - 0 = ASCII code
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-- Designed for Spartan 2 FPGAs
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--
|
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_arith
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-- ieee.std_logic_unsigned
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--
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-- Uses : RAMB4_S8
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--
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-- Author : John E. Kent
|
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--
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-- Email : dilbert57@opencores.org
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--
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--
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-- J.E.Kent
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-- Web : http://opencores.org/project,system09
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-- 18th Oct 2004
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--
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--
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-- Copyright (C) 2004 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
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--
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|
-- This program is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
--
|
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
--
|
|
--===========================================================================--
|
|
-- --
|
|
-- Revision History --
|
|
-- --
|
|
--===========================================================================--
|
|
--
|
|
-- Version Date Author Changes
|
|
--
|
|
-- 0.1 2004-10-18 John Kent Initial Version
|
|
--
|
|
|
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
|
library unisim;
|
use unisim.all;
|
use unisim.all;
|
|
|
entity key_b4 is
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entity keymap_rom is
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Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (8 downto 0);
|
addr : in std_logic_vector (8 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end key_b4;
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end keymap_rom;
|
|
|
architecture rtl of key_b4 is
|
architecture rtl of keymap_rom is
|
|
|
component RAMB4_S8
|
component RAMB4_S8
|
generic (
|
generic (
|
INIT_00, INIT_01, INIT_02, INIT_03,
|
INIT_00, INIT_01, INIT_02, INIT_03,
|
INIT_04, INIT_05, INIT_06, INIT_07,
|
INIT_04, INIT_05, INIT_06, INIT_07,
|
| Line 77... |
Line 123... |
port map ( clk => clk,
|
port map ( clk => clk,
|
en => cs,
|
en => cs,
|
we => we,
|
we => we,
|
rst => rst,
|
rst => rst,
|
addr => addr,
|
addr => addr,
|
di => wdata,
|
di => data_in,
|
do => rdata
|
do => data_out
|
);
|
);
|
|
|
|
|
my_ram_512 : process ( rw )
|
my_ram_512 : process ( rw )
|
begin
|
begin
|
