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--===========================================================================--
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-- --
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-- 2K Byte RAM Block using 4KBit Block RAMs found in the Spartan 2 --
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-- --
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--===========================================================================--
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--
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--
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-- Ram2k.vhd
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-- File name : ram2k_b4.vhd
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--
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--
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-- 2K Byte RAM made out of 4 x 512 byte Block RAMs.
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-- Entity name : ram_2k
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-- John Kent
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--
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-- 11 February 2004
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-- Purpose : 2KB RAM block used for a character text buffer for vdu8
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-- using 4 x 4KBit Block RAMs
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_arith
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-- ieee.std_logic_unsigned
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-- unisim.vcomponents
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--
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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--
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-- Copyright (C) 2004 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- Revision History: --
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--===========================================================================--
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--
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-- Version Date Author Comments
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--
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-- 0.1 2004-02-11 John Kent Initial Version
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-- 0.2 2010-08-27 John Kent Added header
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-- Changed data input & output signals
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (10 downto 0);
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addr : in std_logic_vector (10 downto 0);
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wdata : in std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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rdata : out std_logic_vector (7 downto 0)
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end ram_2k;
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end ram_2k;
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architecture rtl of ram_2k is
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architecture rtl of ram_2k is
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signal we : std_logic;
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signal we : std_logic;
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signal reset : std_logic;
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signal data_out0 : std_logic_vector (7 downto 0);
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signal rdata0 : std_logic_vector (7 downto 0);
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signal data_out1 : std_logic_vector (7 downto 0);
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signal rdata1 : std_logic_vector (7 downto 0);
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signal data_out2 : std_logic_vector (7 downto 0);
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signal rdata2 : std_logic_vector (7 downto 0);
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signal data_out3 : std_logic_vector (7 downto 0);
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signal rdata3 : std_logic_vector (7 downto 0);
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signal ena0 : std_logic;
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signal ena0 : std_logic;
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signal ena1 : std_logic;
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signal ena1 : std_logic;
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signal ena2 : std_logic;
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signal ena2 : std_logic;
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signal ena3 : std_logic;
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signal ena3 : std_logic;
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)
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)
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port map ( clk => clk,
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port map ( clk => clk,
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en => ena0,
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en => ena0,
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we => we,
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we => we,
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rst => reset,
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rst => rst,
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addr(8 downto 0) => addr(8 downto 0),
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addr(8 downto 0) => addr(8 downto 0),
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di(7 downto 0) => wdata(7 downto 0),
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di(7 downto 0) => data_in(7 downto 0),
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do(7 downto 0) => rdata0(7 downto 0)
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do(7 downto 0) => data_out0(7 downto 0)
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);
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);
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MY_RAM1 : RAMB4_S8
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MY_RAM1 : RAMB4_S8
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generic map (
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generic map (
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)
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)
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port map ( clk => clk,
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port map ( clk => clk,
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en => ena1,
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en => ena1,
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we => we,
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we => we,
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rst => reset,
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rst => rst,
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addr(8 downto 0) => addr(8 downto 0),
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addr(8 downto 0) => addr(8 downto 0),
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di(7 downto 0) => wdata(7 downto 0),
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di(7 downto 0) => data_in(7 downto 0),
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do(7 downto 0) => rdata1(7 downto 0)
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do(7 downto 0) => data_out1(7 downto 0)
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);
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);
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MY_RAM2 : RAMB4_S8
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MY_RAM2 : RAMB4_S8
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generic map (
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generic map (
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INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
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INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
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)
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)
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port map ( clk => clk,
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port map ( clk => clk,
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en => ena2,
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en => ena2,
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we => we,
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we => we,
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rst => reset,
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rst => rst,
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addr(8 downto 0) => addr(8 downto 0),
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addr(8 downto 0) => addr(8 downto 0),
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di(7 downto 0) => wdata(7 downto 0),
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di(7 downto 0) => data_in(7 downto 0),
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do(7 downto 0) => rdata2(7 downto 0)
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do(7 downto 0) => data_out2(7 downto 0)
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);
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);
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MY_RAM3 : RAMB4_S8
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MY_RAM3 : RAMB4_S8
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generic map (
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generic map (
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)
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)
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port map ( clk => clk,
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port map ( clk => clk,
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en => ena3,
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en => ena3,
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we => we,
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we => we,
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rst => reset,
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rst => rst,
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addr(8 downto 0) => addr(8 downto 0),
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addr(8 downto 0) => addr(8 downto 0),
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di(7 downto 0) => wdata(7 downto 0),
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di(7 downto 0) => data_in(7 downto 0),
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do(7 downto 0) => rdata3(7 downto 0)
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do(7 downto 0) => data_out3(7 downto 0)
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);
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);
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my_ram_2k : process ( clk, rst, cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
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my_ram_2k : process ( cs, rw, addr, data_out0, data_out1, data_out2, data_out3 )
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begin
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begin
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case addr(10 downto 9) is
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ena0 <= '0';
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when "00" =>
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ena0 <= cs;
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ena1 <= '0';
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ena1 <= '0';
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ena2 <= '0';
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ena2 <= '0';
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ena3 <= '0';
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ena3 <= '0';
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rdata <= rdata0;
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case addr(10 downto 9) is
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when "00" =>
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ena0 <= cs;
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data_out <= data_out0;
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when "01" =>
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when "01" =>
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ena0 <= '0';
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ena1 <= cs;
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ena1 <= cs;
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ena2 <= '0';
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data_out <= data_out1;
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ena3 <= '0';
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rdata <= rdata1;
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when "10" =>
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when "10" =>
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ena0 <= '0';
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ena1 <= '0';
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ena2 <= cs;
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ena2 <= cs;
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ena3 <= '0';
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data_out <= data_out2;
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rdata <= rdata2;
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when "11" =>
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when "11" =>
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ena0 <= '0';
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ena1 <= '0';
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ena2 <= '0';
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ena3 <= cs;
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ena3 <= cs;
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rdata <= rdata3;
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data_out <= data_out3;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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we <= cs and (not rw);
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we <= not rw;
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reset <= rst;
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end process;
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end process;
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end;
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end;
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