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----------------------------------------------------------------
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--===========================================================================--
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-- --
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-- Synthesizable Character Generator using Xilinx RAMB16_S9 Block RAM --
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-- --
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--===========================================================================--
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--
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--
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-- Character generator ROM
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-- File name : char_rom2k_b16.vhd
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--
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--
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-- 7 pixels x 11 rows x 128 characters.
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-- Entity name : char_rom
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--
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-- Purpose : Implements a character generator ROM
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-- using one Xilinx RAMB16_S9 Block RAM
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-- Used by vdu8.vhd in the System09 SoC
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--
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_arith
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--
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-- Uses : RAMB16_S9 (Xilinx 16KBit Block RAM)
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- Description : Characters are 7 pixels x 11 rows x 128 characters
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-- Stored as 8 bits x 16 locations x 128 characters
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Version Date Author Changes
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--
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-- 0.1 2004-10-18 John Kent Initial relaease
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--
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-- 0.2 2010-06-17 John Kent Updated header and description and added GPL
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--
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--
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-- Last Updated
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-- 18th Oct 2004
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-- J. E. Kent.
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----------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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library unisim;
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entity char_rom is
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entity char_rom is
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Port (
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Port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (10 downto 0);
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addr : in std_logic_vector (10 downto 0);
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rdata : out std_logic_vector (7 downto 0);
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rw : in std_logic;
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wdata : in std_logic_vector (7 downto 0)
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data_in : in std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end char_rom;
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end char_rom;
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architecture rtl of char_rom is
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architecture rtl of char_rom is
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INIT_3e => x"0000000070080808040204080808700000000000080808080800080808080800",
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INIT_3e => x"0000000070080808040204080808700000000000080808080800080808080800",
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INIT_3f => x"0000000049224922492249224922490000000000000000000000000046493100"
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INIT_3f => x"0000000049224922492249224922490000000000000000000000000046493100"
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)
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)
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port map (
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port map (
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do => rdata,
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do => data_out,
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dop(0)=> dp,
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dop(0)=> dp,
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addr => addr,
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addr => addr,
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clk => clk,
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clk => clk,
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di => wdata,
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di => data_in,
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dip(0)=> dp,
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dip(0)=> dp,
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en => cs,
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en => cs,
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ssr => rst,
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ssr => rst,
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we => we
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we => we
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);
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);
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