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---------------------------------------------------------
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--===========================================================================--
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-- keymap_rom_slice.vhd
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-- --
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-- Synthesizable PS/2 Keyboard Key map ROM --
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-- --
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--===========================================================================--
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--
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--
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-- PS2 Keycode look up table
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-- File name : keymap_rom_slice.vhd
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-- converts 7 bit key code to ASCII
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--
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-- Address bit 7 = CAPS Lock
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-- Entity name : keymap_rom
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--
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-- Purpose : PS/2 key code look up table for PS/2 Keyboard
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-- Converts 7 bit key code to ASCII
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-- Address bit 8 = Shift
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-- Address bit 8 = Shift
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-- Address bit 7 = CAPS Lock
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-- Address bits 6 - 0 = Key code
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-- Data bits 6 - 0 = ASCII code
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-- Using constant array look up.
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--
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_arith
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-- ieee.std_logic_unsigned
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--
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-- Uses : None
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- Copyright (C) 2004 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Version Date Author Changes
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--
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-- 0.1 2004-10-18 John Kent Initial version
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--
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-- 0.2 2007-01-28 John Kent Made entity compatible with block RAM versions
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--
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-- 0.3 2007-02-03 John Kent Initialized with bit_vector
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--
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-- 0.4 2010-06-17 John Kent Updated header and added GPL
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-- Renamed data_in and data_out signals
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--
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--
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-- J.E.Kent
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-- 18th Oct 2004
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-- 28th Jan 2007 - made entity compatible with block RAM versions.
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-- 3rd Feb 2007 - initialized with Bit_vector
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--
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--
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (8 downto 0);
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addr : in std_logic_vector (8 downto 0);
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rdata : out std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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wdata : in std_logic_vector (7 downto 0)
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end keymap_rom;
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end keymap_rom;
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architecture rtl of keymap_rom is
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architecture rtl of keymap_rom is
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constant width : integer := 8;
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constant memsize : integer := 512;
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signal rvect : std_logic_vector(255 downto 0);
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type rom_array is array(0 to 15) of std_logic_vector (255 downto 0);
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type rom_array is array(0 to 15) of std_logic_vector (255 downto 0);
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constant rom_data : rom_array :=
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constant rom_data : rom_array :=
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(
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(
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x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
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x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
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x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
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x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
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x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
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x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
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x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
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x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
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);
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);
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signal rom_out : std_logic_vector(255 downto 0);
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begin
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process( addr, rom_data, rom_out )
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begin
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begin
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rom_out <= rom_data(conv_integer(addr(8 downto 5)));
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data_out <= rom_out( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
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end;
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rvect <= rom_data(conv_integer(addr(8 downto 5)));
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rdata <= rvect( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
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end architecture rtl;
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end architecture rtl;
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No newline at end of file
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No newline at end of file
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