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--===========================================================================--
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-- --
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-- Synthesizable 2K RAM using Xilinx RAMB16_S9 Block RAM --
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-- --
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--===========================================================================--
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--
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-- File name : ram2k_b16.vhd
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--
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-- Entity name : ram_2k
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--
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-- Purpose : Implements 2KBytes of RAM using one Xilinx RAMB16_S9 Block RAM
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-- Essentially a wrapper for a 2KByte RAM block for different
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-- technology FPGAs. Used in vdu8.vhd for the System09 SoC as a
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-- character buffer and attribute RAM. Initiatized with rubbish
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-- so that the VDU displays random characters on start up to
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-- indicate it is working correctly.
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--
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_arith
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--
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-- Uses : RAMB16_S9 (Xilinx 16KBit Block RAM)
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- Description : Block RAM instatiation
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--
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-- Copyright (C) 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Version Date Author Changes
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--
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-- 0.1 2010-06-17 John Kent Added GPL and header
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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entity ram_2k is
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entity ram_2k is
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Port (
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Port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (10 downto 0);
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addr : in std_logic_vector (10 downto 0);
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rdata : out std_logic_vector (7 downto 0);
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rw : in std_logic;
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wdata : in std_logic_vector (7 downto 0)
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data_in : in std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end ram_2k;
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end ram_2k;
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architecture rtl of ram_2k is
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architecture rtl of ram_2k is
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INIT_3E => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
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INIT_3E => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
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INIT_3F => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
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INIT_3F => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
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)
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)
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port map (
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port map (
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do => rdata,
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do => data_out,
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dop(0) => dp,
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dop(0) => dp,
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addr => addr,
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addr => addr,
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clk => clk,
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clk => clk,
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di => wdata,
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di => data_in,
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dip(0) => dp,
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dip(0) => dp,
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en => cs,
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en => cs,
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ssr => rst,
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ssr => rst,
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we => we
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we => we
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);
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);
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