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--===========================================================================--
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-- --
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-- sys09bug_s3e_rom2k_b16.vhd - Sys09bug monitor ROM for the Spartan 3E500 --
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-- --
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--===========================================================================--
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--
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--
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-- SYS09BUG MONITOR ROM FOR SYSTEM09 SPARTAN3E
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-- File name : sys09bug_s3e_rom2k_b16.vhd
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-- John Kent
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--
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-- 8th January 2008
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-- Entity name : mon_rom
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--
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-- Purpose : Implements 2K Monitor ROM for System09
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-- using 1 x Spartan 3E RAMB16_S9 block ram
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-- Used in the Digilent Spartan 3E500 System09 design
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_arith
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-- unisim.vcomponents
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--
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-- Uses : RAMB16_S9
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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--
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-- Copyright (C) 2008 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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-- Version Author Date Changes
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-- 0.1 John Kent 2008-01-08 Initial Version
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-- 0.2 John Kent 2010-09-14 Added Header
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-- renamed rdata & wdata to data_out & data_in
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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library unisim;
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library unisim;
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entity mon_rom is
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entity mon_rom is
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Port (
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Port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (10 downto 0);
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addr : in std_logic_vector (10 downto 0);
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rdata : out std_logic_vector (7 downto 0);
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rw : in std_logic;
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wdata : in std_logic_vector (7 downto 0)
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data_in : in std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end mon_rom;
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end mon_rom;
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architecture rtl of mon_rom is
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architecture rtl of mon_rom is
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INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3f => x"E2FEEEFEFEFEFAFEF6FEF2FE02FFEEFE00000000000000000000000000000000"
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INIT_3f => x"E2FEEEFEFEFEFAFEF6FEF2FE02FFEEFE00000000000000000000000000000000"
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)
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)
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port map (
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port map (
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do => rdata,
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do => data_out,
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dop(0) => dp,
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dop(0) => dp,
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addr => addr,
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addr => addr,
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clk => clk,
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clk => clk,
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di => wdata,
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di => data_in,
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dip(0) => dp,
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dip(0) => dp,
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en => cs,
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en => cs,
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ssr => rst,
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ssr => rst,
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we => we
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we => we
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);
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);
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