| Line 1... |
Line 1... |
--===========================================================================----
|
--=============================================================================--
|
|
-- --
|
|
-- System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
|
|
-- --
|
|
--=============================================================================--
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--
|
--
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
|
--
|
--
|
-- www.OpenCores.Org - September 2003
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-- File name : System09_Digilent_3S200.vhd
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-- This core adheres to the GNU public license
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|
--
|
--
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-- File name : System09.vhd
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-- Entity name : System09
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--
|
--
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-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Purpose : Top level file for 6809 compatible system on a chip
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-- Designed with Xilinx XC3S200 Spartan 3 FPGA.
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-- Designed with Xilinx XC3S200 Spartan 3 FPGA.
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-- Implemented With Digilent Xilinx Starter FPGA board,
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-- Implemented With Digilent Xilinx Starter FPGA board,
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_arith
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-- ieee.std_logic_arith
|
-- ieee.numeric_std
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-- ieee.numeric_std
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--
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--
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-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Monitor ROM
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-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core
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-- cpu09 (cpu09.vhd) CPU core
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-- dat_ram (..\VHDL\datram.vhd) Dynamic Address Translation
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-- dat_ram (datram.vhd) Dynamic Address Translation
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-- SYS09BUG_F800 (..\Spartan3\sys093s3_b16.vhd) Monitor ROM
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-- acia_6850 (acia_6850.vhd) ACIA (UART)
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-- acia6850 (..\VHDL\acia6850.vhd) ACIA (UART)
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-- (acia_rx.vhd)
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-- ACIA_Clock (..\VHDL\ACIA_Clock.vhd) ACIA Baud Rate Clock Divider
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-- (acia_tx.vhd)
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-- keyboard (..\VHDL\keyboard.vhd) PS/2 Keyboard register interface
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-- keyboard (keyboard.vhd) PS/2 Keyboard
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-- ps2_keyboard (..\VHDL\ps2_keyboard.vhd) PS/2 Keyboard interface logic
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-- (ps2_keyboard.vhd)
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-- keymap_rom (..\Spartan2\keymap_rom.vhd) PS/2 Keyboard key code look up table
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-- (keymap_rom)
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-- vdu8 (..\VHDL\vdu8.vhd) Video Display Unit
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-- vdu8 (vdu8.vhd) Video Display Unit
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-- (..\Spartan3\char_rom2K_b16.vhd) Character Generator ROM (B16_RAM)
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-- (char_rom2K_b16.vhd)
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-- (..\Spartan3\ram2k_b16.vhd) Text & Attribute RAM Buffer
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-- (ram2k_b16.vhd)
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-- seven_segment (..\VHDL\SevenSegment.vhd) Seven Segment Display
|
-- seven_segment (SevenSegment.vhd) Seven Segment Display
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
|
-- dilbert57@opencores.org
|
--
|
--
|
--===========================================================================----
|
-- Memory Map :
|
|
--
|
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-- $0000 - $DFFF System RAM (256K Mapped via DAT)
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-- $E000 - ACIA (SWTPc)
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-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
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-- $E020 - Keyboard
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-- $E030 - VDU
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-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
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-- $E050 - Timer
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-- $E060 - Reserved for Bus Trap (Hardware Breakpoint Logic)
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-- $E070 - Reserved for Trace Buffer
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-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
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-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
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-- $E0A0 - Switches in / LEDS out
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-- $E0B0 - 7 Segment display
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-- $E0C0 - Reserved
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|
-- $E0D0 - Reserved
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-- $E0E0 - Reserved
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-- $E0F0 - Reserved
|
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-- $E100 - $E13F Reserved IDE / Compact Flash Card
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-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
|
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-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
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-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
|
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-- $E200 - $EFFF Reserved for Future I/O
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-- $F000 - $F7FF RAM for Sys09bug monitor extensions
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-- $F800 - $FFFF Sys09bug ROM (Read only)
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-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
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--
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
|
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
|
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
|
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
|
|
--===========================================================================--
|
--
|
--
|
-- Revision History:
|
-- Revision History:
|
|
--
|
--===========================================================================--
|
--===========================================================================--
|
|
--
|
-- Version 0.1 - 20 March 2003
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-- Version 0.1 - 20 March 2003
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-- Version 0.2 - 30 March 2003
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-- Version 0.2 - 30 March 2003
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-- Version 0.3 - 29 April 2003
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-- Version 0.3 - 29 April 2003
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-- Version 0.4 - 29 June 2003
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-- Version 0.4 - 29 June 2003
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--
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--
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| Line 90... |
Line 137... |
--
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--
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-- Version 2.4 - 31 January 2008 - John Kent
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-- Version 2.4 - 31 January 2008 - John Kent
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-- ACIA does not appear to work.
|
-- ACIA does not appear to work.
|
-- Made RAM OE and WE strobes synchonous to sys_clk
|
-- Made RAM OE and WE strobes synchonous to sys_clk
|
--
|
--
|
|
-- Version 2.5 - 23rd Feburary 2009 - John Kent
|
|
-- Implemented recommendation to remove vga_clk clock buffer
|
|
--
|
|
-- Version 2.6 - 5th september 2010 - John Kent
|
|
-- Renamed ACIA_6850 to acia6850
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|
-- Updated generics on VDU8
|
|
-- Shortened the "keyboard" label
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|
-- Fixed up address label on CPU09
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-- Removed Flex RAM
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-- Map RAM at $F000 - $F7FF
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--
|
--===========================================================================--
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--===========================================================================--
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library ieee;
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library ieee;
|
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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| Line 150... |
Line 208... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture my_computer of my_system09 is
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architecture my_computer of my_system09 is
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- constants
|
-- constants
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
|
constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
|
constant VGA_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
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constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
|
constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock
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constant CPU_CLK_FREQ : integer := 25000000; -- CPU Clock
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constant BAUD_Rate : integer := 57600; -- Baud Rate
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constant BAUD_Rate : integer := 57600; -- Baud Rate
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constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
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constant ACIA_CLK_FREQ : integer := BAUD_Rate * 16;
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|
|
type hold_state_type is ( hold_release_state, hold_request_state );
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type hold_state_type is ( hold_release_state, hold_request_state );
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|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
-- CPU Interface signals
|
|
signal cpu_clk : Std_Logic;
|
|
signal cpu_rst : Std_Logic;
|
|
signal cpu_rw : std_logic;
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|
signal cpu_vma : std_logic;
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|
signal cpu_halt : std_logic;
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|
signal cpu_hold : std_logic;
|
|
signal cpu_firq : std_logic;
|
|
signal cpu_irq : std_logic;
|
|
signal cpu_nmi : std_logic;
|
|
signal cpu_addr : std_logic_vector(15 downto 0);
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|
signal cpu_data_in : std_logic_vector(7 downto 0);
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signal cpu_data_out : std_logic_vector(7 downto 0);
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|
|
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-- Dynamic Address Translation
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|
signal dat_cs : std_logic;
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signal dat_addr : std_logic_vector(7 downto 0);
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|
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-- BOOT ROM
|
-- BOOT ROM
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signal rom_cs : Std_logic;
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signal rom_cs : Std_logic;
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
-- FLEX9 RAM
|
|
signal flex_cs : Std_logic;
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|
signal flex_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
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-- ACIA Interface signals
|
-- ACIA Interface signals
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signal acia_clk : std_logic;
|
signal acia_clk : std_logic;
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signal acia_data_out : Std_Logic_Vector(7 downto 0);
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signal acia_cs : Std_Logic;
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signal acia_cs : Std_Logic;
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signal acia_data_out : Std_Logic_Vector(7 downto 0);
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signal acia_irq : Std_Logic;
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signal acia_irq : Std_Logic;
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signal acia_rxd : Std_Logic;
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signal acia_rxd : Std_Logic;
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signal acia_txd : Std_Logic;
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signal acia_txd : Std_Logic;
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signal acia_dcd_n : Std_Logic;
|
signal acia_dcd_n : Std_Logic;
|
-- signal acia_rts_n : Std_Logic;
|
-- signal acia_rts_n : Std_Logic;
|
signal acia_cts_n : Std_Logic;
|
signal acia_cts_n : Std_Logic;
|
|
|
-- keyboard port
|
-- keyboard port
|
signal keyboard_data_out : std_logic_vector(7 downto 0);
|
signal kbd_data_out : std_logic_vector(7 downto 0);
|
signal keyboard_cs : std_logic;
|
signal kbd_cs : std_logic;
|
signal keyboard_irq : std_logic;
|
signal kbd_irq : std_logic;
|
|
|
-- LEDs
|
-- LEDs
|
signal leds_data_out : std_logic_vector(7 downto 0);
|
signal leds_data_out : std_logic_vector(7 downto 0);
|
signal leds_cs : std_logic;
|
signal leds_cs : std_logic;
|
|
|
|
-- Video Display Unit
|
|
signal vdu_cs : std_logic;
|
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
|
signal vga_clk : std_logic;
|
|
|
|
-- 7 Segment Display
|
|
signal seg_cs : std_logic;
|
|
signal seg_data_out : std_logic_vector(7 downto 0);
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram1_ce : std_logic;
|
signal ram1_ce : std_logic;
|
signal ram1_ub : std_logic;
|
signal ram1_ub : std_logic;
|
| Line 201... |
Line 283... |
signal ram2_ub : std_logic;
|
signal ram2_ub : std_logic;
|
signal ram2_lb : std_logic;
|
signal ram2_lb : std_logic;
|
signal ram_we : std_logic;
|
signal ram_we : std_logic;
|
signal ram_oe : std_logic;
|
signal ram_oe : std_logic;
|
|
|
-- CPU Interface signals
|
|
signal cpu_reset : Std_Logic;
|
|
signal cpu_clk : Std_Logic;
|
|
signal cpu_rw : std_logic;
|
|
signal cpu_vma : std_logic;
|
|
signal cpu_halt : std_logic;
|
|
signal cpu_hold : std_logic;
|
|
signal cpu_firq : std_logic;
|
|
signal cpu_irq : std_logic;
|
|
signal cpu_nmi : std_logic;
|
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
|
signal cpu_data_out : std_logic_vector(7 downto 0);
|
|
|
|
-- Dynamic Address Translation
|
|
signal dat_cs : std_logic;
|
|
signal dat_addr : std_logic_vector(7 downto 0);
|
|
|
|
-- Video Display Unit
|
|
signal vdu_cs : std_logic;
|
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
|
signal vga_clk : std_logic;
|
|
|
|
-- 7 Segment Display
|
|
signal seg_cs : std_logic;
|
|
signal seg_data_out : std_logic_vector(7 downto 0);
|
|
|
|
-- System Clock Prescaler
|
-- System Clock Prescaler
|
signal clk_count : std_logic;
|
signal clk_count : std_logic;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
| Line 241... |
Line 296... |
|
|
component cpu09
|
component cpu09
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
rw : out std_logic; -- Asynchronous memory interface
|
|
vma : out std_logic;
|
vma : out std_logic;
|
address : out std_logic_vector(15 downto 0);
|
addr : out std_logic_vector(15 downto 0);
|
|
rw : out std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
halt : in std_logic;
|
halt : in std_logic;
|
hold : in std_logic;
|
hold : in std_logic;
|
irq : in std_logic;
|
irq : in std_logic;
|
nmi : in std_logic;
|
nmi : in std_logic;
|
firq : in std_logic
|
firq : in std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- 4KByte Block RAM Monitor ROM
|
-- Dynamic Address Translation Registers
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component mon_rom
|
component dat_ram
|
Port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (11 downto 0);
|
addr_lo : in std_logic_vector(3 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
addr_hi : in std_logic_vector(3 downto 0);
|
data_in : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector(7 downto 0);
|
|
data_out : out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- 8KBytes Block RAM for FLEX9
|
-- 4KByte Block RAM Monitor ROM
|
-- $C000 - $DFFF
|
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component flex_ram
|
component SYS09BUG_F800
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (12 downto 0);
|
addr : in std_logic_vector (10 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
|
data_in : in std_logic_vector (7 downto 0)
|
|
);
|
|
end component;
|
|
|
|
----------------------------------------
|
|
--
|
|
-- Dynamic Address Translation Registers
|
|
--
|
|
----------------------------------------
|
|
component dat_ram
|
|
port (
|
|
clk : in std_logic;
|
|
rst : in std_logic;
|
|
cs : in std_logic;
|
|
rw : in std_logic;
|
|
addr_lo : in std_logic_vector(3 downto 0);
|
|
addr_hi : in std_logic_vector(3 downto 0);
|
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0)
|
data_out : out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 314... |
Line 350... |
--
|
--
|
-- 6850 ACIA
|
-- 6850 ACIA
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_6850
|
component acia6850
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock
|
clk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic; -- ACIA Chip Select
|
cs : in Std_Logic; -- ACIA Chip Select
|
rw : in Std_Logic; -- Read / Not Write
|
rw : in Std_Logic; -- Read / Not Write
|
|
addr : in Std_Logic; -- Register Select
|
|
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
|
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
irq : out Std_Logic; -- Interrupt
|
irq : out Std_Logic; -- Interrupt
|
Addr : in Std_Logic; -- Register Select
|
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
|
RxC : in Std_Logic; -- Receive Baud Clock
|
RxC : in Std_Logic; -- Receive Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
RxD : in Std_Logic; -- Receive Data
|
RxD : in Std_Logic; -- Receive Data
|
TxD : out Std_Logic; -- Transmit Data
|
TxD : out Std_Logic; -- Transmit Data
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
| Line 342... |
Line 378... |
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_Clock
|
component ACIA_Clock
|
generic (
|
generic (
|
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
|
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
|
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
|
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
|
);
|
);
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock Input
|
clk : in Std_Logic; -- System Clock Input
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
acia_clk : out Std_logic -- ACIA Clock output
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- PS/2 Keyboard
|
-- PS/2 Keyboard
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component keyboard
|
component keyboard
|
generic(
|
generic(
|
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
|
KBD_CLK_FREQ : integer := CPU_CLK_FREQ
|
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
|
addr : in std_logic;
|
addr : in std_logic;
|
|
rw : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic;
|
irq : out std_logic;
|
kbd_clk : inout std_logic;
|
kbd_clk : inout std_logic;
|
kbd_data : inout std_logic
|
kbd_data : inout std_logic
|
| Line 383... |
Line 418... |
-- Video Display Unit.
|
-- Video Display Unit.
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
component vdu8
|
component vdu8
|
generic(
|
generic(
|
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
|
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
|
VGA_CLOCK_FREQUENCY : integer := VGA_Clock_Frequency; -- HZ
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
|
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
|
VGA_LINES_PER_CHAR : integer := 16; -- LINES
|
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
|
VGA_VER_SYNC : integer := 1; -- LINES
|
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
|
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
|
|
);
|
);
|
port(
|
port(
|
-- control register interface
|
-- control register interface
|
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
|
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
|
vdu_rst : in std_logic;
|
vdu_rst : in std_logic;
|
| Line 427... |
Line 461... |
component seven_segment is
|
component seven_segment is
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
|
addr : in std_logic_vector(1 downto 0);
|
addr : in std_logic_vector(1 downto 0);
|
|
rw : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
segments : out std_logic_vector(7 downto 0);
|
segments : out std_logic_vector(7 downto 0);
|
digits : out std_logic_vector(3 downto 0)
|
digits : out std_logic_vector(3 downto 0)
|
);
|
);
|
| Line 450... |
Line 484... |
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
my_cpu : cpu09 port map (
|
my_cpu : cpu09 port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
rw => cpu_rw,
|
|
vma => cpu_vma,
|
vma => cpu_vma,
|
address => cpu_addr(15 downto 0),
|
addr => cpu_addr(15 downto 0),
|
|
rw => cpu_rw,
|
data_in => cpu_data_in,
|
data_in => cpu_data_in,
|
data_out => cpu_data_out,
|
data_out => cpu_data_out,
|
halt => cpu_halt,
|
halt => cpu_halt,
|
hold => cpu_hold,
|
hold => cpu_hold,
|
irq => cpu_irq,
|
irq => cpu_irq,
|
nmi => cpu_nmi,
|
nmi => cpu_nmi,
|
firq => cpu_firq
|
firq => cpu_firq
|
);
|
);
|
|
|
my_rom : mon_rom port map (
|
|
clk => cpu_clk,
|
|
rst => cpu_reset,
|
|
cs => rom_cs,
|
|
rw => '1',
|
|
addr => cpu_addr(11 downto 0),
|
|
data_out => rom_data_out,
|
|
data_in => cpu_data_out
|
|
);
|
|
|
|
my_flex : flex_ram port map (
|
|
clk => cpu_clk,
|
|
rst => cpu_reset,
|
|
cs => flex_cs,
|
|
rw => cpu_rw,
|
|
addr => cpu_addr(12 downto 0),
|
|
data_out => flex_data_out,
|
|
data_in => cpu_data_out
|
|
);
|
|
|
|
my_dat : dat_ram port map (
|
my_dat : dat_ram port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => dat_cs,
|
cs => dat_cs,
|
rw => cpu_rw,
|
|
addr_hi => cpu_addr(15 downto 12),
|
addr_hi => cpu_addr(15 downto 12),
|
addr_lo => cpu_addr(3 downto 0),
|
addr_lo => cpu_addr(3 downto 0),
|
|
rw => cpu_rw,
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => dat_addr(7 downto 0)
|
data_out => dat_addr(7 downto 0)
|
);
|
);
|
|
|
my_acia : ACIA_6850 port map (
|
my_rom : SYS09BUG_F800 port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
|
cs => rom_cs,
|
|
rw => '1',
|
|
addr => cpu_addr(10 downto 0),
|
|
data_in => cpu_data_out,
|
|
data_out => rom_data_out
|
|
);
|
|
|
|
my_acia : acia6850 port map (
|
|
clk => cpu_clk,
|
|
rst => cpu_rst,
|
cs => acia_cs,
|
cs => acia_cs,
|
|
addr => cpu_addr(0),
|
rw => cpu_rw,
|
rw => cpu_rw,
|
|
data_in => cpu_data_out,
|
|
data_out => acia_data_out,
|
irq => acia_irq,
|
irq => acia_irq,
|
Addr => cpu_addr(0),
|
|
Datain => cpu_data_out,
|
|
DataOut => acia_data_out,
|
|
RxC => acia_clk,
|
RxC => acia_clk,
|
TxC => acia_clk,
|
TxC => acia_clk,
|
RxD => acia_rxd,
|
RxD => acia_rxd,
|
TxD => acia_txd,
|
TxD => acia_txd,
|
DCD_n => acia_dcd_n,
|
DCD_n => acia_dcd_n,
|
| Line 520... |
Line 544... |
-- ACIA Clock
|
-- ACIA Clock
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_Clock_Frequency => SYS_Clock_Frequency,
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
ACIA_Clock_Frequency => ACIA_Clock_Frequency
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => sys_clk,
|
clk => sys_clk,
|
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
| Line 536... |
Line 560... |
-- PS/2 Keyboard Interface
|
-- PS/2 Keyboard Interface
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_keyboard : keyboard
|
my_keyboard : keyboard
|
generic map (
|
generic map (
|
KBD_Clock_Frequency => CPU_Clock_frequency
|
KBD_CLK_FREQ => CPU_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => keyboard_cs,
|
cs => kbd_cs,
|
rw => cpu_rw,
|
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
|
rw => cpu_rw,
|
data_in => cpu_data_out(7 downto 0),
|
data_in => cpu_data_out(7 downto 0),
|
data_out => keyboard_data_out(7 downto 0),
|
data_out => kbd_data_out(7 downto 0),
|
irq => keyboard_irq,
|
irq => kbd_irq,
|
kbd_clk => ps2c,
|
kbd_clk => ps2c,
|
kbd_data => ps2d
|
kbd_data => ps2d
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
| Line 558... |
Line 582... |
-- Video Display Unit instantiation
|
-- Video Display Unit instantiation
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_vdu : vdu8
|
my_vdu : vdu8
|
generic map(
|
generic map(
|
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- 25MHZ
|
VGA_CLOCK_FREQUENCY => VGA_Clock_Frequency, -- HZ
|
VGA_HOR_CHARS => 80, -- CHARACTERS 25.6us
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_HOR_CHAR_PIXELS => 8, -- PIXELS 0.32us
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_HOR_FRONT_PORCH => 16, -- PIXELS 0.64us
|
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS 3.84us
|
VGA_LINES_PER_CHAR => 16, -- LINES
|
VGA_HOR_BACK_PORCH => 48, -- PIXELS 1.92us
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
VGA_VER_CHARS => 25, -- CHARACTERS 12.8ms
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_VER_CHAR_LINES => 16, -- LINES 0.512ms
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_VER_FRONT_PORCH => 10, -- LINES 0.320ms
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_SYNC => 2, -- LINES 0.064ms
|
VGA_VER_SYNC => 1, -- LINES
|
VGA_VER_BACK_PORCH => 34 -- LINES 1.088ms
|
VGA_VER_FRONT_PORCH => 36 -- LINES
|
|
)
|
)
|
port map(
|
port map(
|
|
|
-- Control Registers
|
-- Control Registers
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
vdu_rst => cpu_reset,
|
vdu_rst => cpu_rst,
|
vdu_cs => vdu_cs,
|
vdu_cs => vdu_cs,
|
vdu_rw => cpu_rw,
|
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_addr => cpu_addr(2 downto 0),
|
|
vdu_rw => cpu_rw,
|
vdu_data_in => cpu_data_out,
|
vdu_data_in => cpu_data_out,
|
vdu_data_out => vdu_data_out,
|
vdu_data_out => vdu_data_out,
|
|
|
-- vga port connections
|
-- vga port connections
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
| Line 600... |
Line 623... |
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
my_seg : seven_segment port map (
|
my_seg : seven_segment port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => seg_cs,
|
cs => seg_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(1 downto 0),
|
addr => cpu_addr(1 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => seg_data_out,
|
data_out => seg_data_out,
|
segments => segments,
|
segments => segments,
|
digits => digits
|
digits => digits
|
);
|
);
|
|
|
|
--vga_clk_buffer : BUFG port map(
|
|
-- i => clk_count,
|
|
-- o => vga_clk
|
|
-- );
|
|
|
vga_clk_buffer : BUFG port map(
|
vga_clk <= cpu_clk;
|
i => clk_count,
|
|
o => vga_clk
|
|
);
|
|
|
|
cpu_clk_buffer : BUFG port map(
|
cpu_clk_buffer : BUFG port map(
|
i => clk_count,
|
i => clk_count,
|
o => cpu_clk
|
o => cpu_clk
|
);
|
);
|
| Line 644... |
Line 668... |
|
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
dat_cs, dat_addr,
|
dat_cs, dat_addr,
|
rom_data_out,
|
rom_data_out,
|
acia_data_out,
|
acia_data_out,
|
keyboard_data_out,
|
kbd_data_out,
|
vdu_data_out,
|
vdu_data_out,
|
seg_data_out,
|
seg_data_out,
|
leds_data_out,
|
leds_data_out,
|
flex_data_out,
|
|
ram_data_out
|
ram_data_out
|
)
|
)
|
begin
|
begin
|
cpu_data_in <= (others=>'0');
|
cpu_data_in <= (others=>'0');
|
dat_cs <= '0';
|
dat_cs <= '0';
|
rom_cs <= '0';
|
rom_cs <= '0';
|
acia_cs <= '0';
|
acia_cs <= '0';
|
keyboard_cs <= '0';
|
kbd_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
seg_cs <= '0';
|
seg_cs <= '0';
|
leds_cs <= '0';
|
leds_cs <= '0';
|
flex_cs <= '0';
|
|
ram_cs <= '0';
|
ram_cs <= '0';
|
-- timer_cs <= '0';
|
-- timer_cs <= '0';
|
-- trap_cs <= '0';
|
-- trap_cs <= '0';
|
-- pb_cs <= '0';
|
-- pb_cs <= '0';
|
-- ide_cs <= '0';
|
-- ide_cs <= '0';
|
| Line 678... |
Line 700... |
rom_cs <= cpu_vma; -- read ROM
|
rom_cs <= cpu_vma; -- read ROM
|
--
|
--
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
--
|
--
|
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
|
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
|
|
if cpu_addr(11) = '1' then
|
--
|
--
|
-- Monitor ROM $F000 - $FFFF
|
-- Monitor ROM $F800 - $FFFF
|
--
|
--
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
rom_cs <= cpu_vma; -- read ROM
|
rom_cs <= cpu_vma; -- read ROM
|
|
else
|
|
--
|
|
-- SRAM $F000 - $F7FF
|
|
--
|
|
cpu_data_in <= ram_data_out;
|
|
ram_cs <= cpu_vma;
|
|
end if;
|
--
|
--
|
-- IO Devices $E000 - $EFFF
|
-- IO Devices $E000 - $EFFF
|
--
|
--
|
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
|
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
|
case cpu_addr(11 downto 8) is
|
case cpu_addr(11 downto 8) is
|
| Line 709... |
Line 738... |
|
|
--
|
--
|
-- Keyboard port ($E020 - $E02F)
|
-- Keyboard port ($E020 - $E02F)
|
--
|
--
|
when "0010" =>
|
when "0010" =>
|
cpu_data_in <= keyboard_data_out;
|
cpu_data_in <= kbd_data_out;
|
keyboard_cs <= cpu_vma;
|
kbd_cs <= cpu_vma;
|
|
|
--
|
--
|
-- VDU port ($E030 - $E03F)
|
-- VDU port ($E030 - $E03F)
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
| Line 763... |
Line 792... |
|
|
when others => -- $EXC0 to $EXFF
|
when others => -- $EXC0 to $EXFF
|
null;
|
null;
|
end case;
|
end case;
|
--
|
--
|
-- XST-3.0 Peripheral Bus goes here
|
-- $E100 to $EFFF reserved for future use
|
-- $E100 to $E1FF
|
|
-- Four devices
|
|
-- IDE, Ethernet, Slot1, Slot2
|
|
--
|
|
-- when "0001" =>
|
|
-- cpu_data_in <= pb_data_out;
|
|
-- pb_cs <= cpu_vma;
|
|
-- case cpu_addr(7 downto 6) is
|
|
--
|
|
-- IDE Interface $E100 to $E13F
|
|
--
|
|
-- when "00" =>
|
|
-- ide_cs <= cpu_vma;
|
|
--
|
|
-- Ethernet Interface $E140 to $E17F
|
|
--
|
|
-- when "01" =>
|
|
-- ether_cs <= cpu_vma;
|
|
--
|
|
-- Slot 1 Interface $E180 to $E1BF
|
|
--
|
|
-- when "10" =>
|
|
-- slot1_cs <= cpu_vma;
|
|
--
|
|
-- Slot 2 Interface $E1C0 to $E1FF
|
|
--
|
|
-- when "11" =>
|
|
-- slot2_cs <= cpu_vma;
|
|
--
|
|
-- Nothing else
|
|
--
|
|
-- when others =>
|
|
-- null;
|
|
-- end case;
|
|
--
|
|
-- $E200 to $EFFF reserved for future use
|
|
--
|
--
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
--
|
--
|
-- FLEX RAM $0C000 - $0DFFF
|
|
--
|
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
|
cpu_data_in <= flex_data_out;
|
|
flex_cs <= cpu_vma;
|
|
--
|
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
else
|
else
|
cpu_data_in <= ram_data_out;
|
cpu_data_in <= ram_data_out;
|
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
| Line 824... |
Line 811... |
|
|
--
|
--
|
-- 1M byte SRAM Control
|
-- 1M byte SRAM Control
|
-- Processes to read and write memory based on bus signals
|
-- Processes to read and write memory based on bus signals
|
--
|
--
|
ram_process: process( cpu_reset, sys_clk,
|
ram_process: process( cpu_rst, sys_clk,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
|
dat_addr, ram_cs,
|
dat_addr, ram_cs,
|
ram1_ce, ram1_ub, ram1_lb, ram1_data,
|
ram1_ce, ram1_ub, ram1_lb, ram1_data,
|
ram2_ce, ram2_ub, ram2_lb, ram2_data,
|
ram2_ce, ram2_ub, ram2_lb, ram2_data,
|
ram_we, ram_oe )
|
ram_we, ram_oe )
|
begin
|
begin
|
--
|
--
|
-- ram_hold signal helps
|
-- ram_hold signal helps
|
--
|
--
|
if( cpu_reset = '1' ) then
|
if( cpu_rst = '1' ) then
|
ram_we <= '0';
|
ram_we <= '0';
|
ram_oe <= '0';
|
ram_oe <= '0';
|
--
|
--
|
-- Clock Hold on rising edge
|
-- Clock Hold on rising edge
|
--
|
--
|
| Line 909... |
Line 896... |
end process;
|
end process;
|
|
|
--
|
--
|
-- LEDS output register
|
-- LEDS output register
|
--
|
--
|
leds_output : process( cpu_clk, cpu_reset, switches )
|
leds_output : process( cpu_clk, cpu_rst, switches )
|
begin
|
begin
|
if cpu_reset = '1' then
|
if cpu_rst = '1' then
|
leds <= "00000000";
|
leds <= "00000000";
|
elsif cpu_clk'event and cpu_clk='0' then
|
elsif cpu_clk'event and cpu_clk='0' then
|
if leds_cs = '1' and cpu_rw = '0' then
|
if leds_cs = '1' and cpu_rw = '0' then
|
leds <= cpu_data_out;
|
leds <= cpu_data_out;
|
end if;
|
end if;
|
| Line 924... |
Line 911... |
end process;
|
end process;
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( rst_sw,
|
interrupts : process( sys_clk, rst_sw,
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acia_irq,
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acia_irq, kbd_irq, nmi_sw )
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keyboard_irq,
|
|
nmi_sw
|
|
)
|
|
begin
|
begin
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if sys_clk'event and sys_clk = '1' then
|
if sys_clk'event and sys_clk = '1' then
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cpu_reset <= rst_sw; -- CPU reset is active high
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cpu_rst <= rst_sw; -- CPU reset is active high
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end if;
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end if;
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cpu_firq <= keyboard_irq;
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cpu_firq <= kbd_irq;
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cpu_nmi <= nmi_sw;
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cpu_nmi <= nmi_sw;
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cpu_irq <= acia_irq;
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cpu_irq <= acia_irq;
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cpu_halt <= '0';
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cpu_halt <= '0';
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cpu_hold <= '0';
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cpu_hold <= '0';
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end process;
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end process;
|
