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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_3S200/] [System09_Digilent_3S200.vhd] - Diff between revs 99 and 111

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Rev 99 Rev 111
Line 155... Line 155...
   use ieee.std_logic_1164.all;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
   use ieee.numeric_std.all;
 
 
entity my_system09 is
entity system09 is
  port(
  port(
    sys_clk     : in  Std_Logic;  -- System Clock input
    sys_clk     : in  Std_Logic;  -- System Clock input
         rst_sw    : in  Std_logic;  -- Master Reset input (active high)
         rst_sw    : in  Std_logic;  -- Master Reset input (active high)
         nmi_sw      : in  Std_logic;
         nmi_sw      : in  Std_logic;
 
 
Line 199... Line 199...
 
 
         -- seven segment display
         -- seven segment display
         segments    : out std_logic_vector(7 downto 0);
         segments    : out std_logic_vector(7 downto 0);
         digits      : out std_logic_vector(3 downto 0)
         digits      : out std_logic_vector(3 downto 0)
         );
         );
end my_system09;
end system09;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture for System09
-- Architecture for System09
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture my_computer of my_system09 is
architecture my_computer of system09 is
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- constants
  -- constants
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
  constant SYS_CLK_FREQ  : integer := 50000000;  -- FPGA System Clock
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock
  constant VGA_CLK_FREQ  : integer := 25000000;  -- VGA Pixel Clock

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