| Line 1... |
Line 1... |
-- $Id: System09_Digilent_3S500E.vhd,v 1.3.2.1 2008/04/08 14:59:48 davidgb Exp $
|
-- $Id: System09_Digilent_3S500E.vhd,v 1.3.2.1 2008/04/08 14:59:48 davidgb Exp $
|
--===========================================================================----
|
--===========================================================================
|
--
|
--
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
-- System09 - SoC for the Digilent Spartan 3E Starter board
|
--
|
--
|
--===========================================================================----
|
--===========================================================================
|
--
|
|
-- This core adheres to the GNU public license
|
|
--
|
--
|
-- File name : System09_Digilent_3S500E.vhd
|
-- File name : System09_Digilent_3S500E.vhd
|
--
|
--
|
|
-- Entity name : my_system09
|
|
--
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Designed with Xilinx XC3S500E Spartan 3E FPGA.
|
-- Designed with Xilinx XC3S500E Spartan 3E FPGA.
|
-- Implemented With Digilent Xilinx Starter FPGA board,
|
-- Implemented With Digilent Xilinx Starter FPGA board,
|
--
|
--
|
-- Dependencies : ieee.Std_Logic_1164
|
-- Dependencies : ieee.Std_Logic_1164
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_arith
|
-- ieee.std_logic_arith
|
-- ieee.numeric_std
|
-- ieee.numeric_std
|
--
|
--
|
-- Uses : mon_rom (kbug_rom2k.vhd) Monitor ROM
|
-- Uses : clock_div (../vhdl/clock_div.vhd) System clock divider
|
-- cpu09 (cpu09.vhd) CPU core
|
-- flasher (../vhdl/flasher.vhd) LED flasher
|
-- miniuart (minitUART3.vhd) ACIA / MiniUART
|
-- ram_32k (../Spartan3/ram32k_b16.vhd) 32K block RAM
|
-- (rxunit3.vhd)
|
-- cpu09 (../vhdl/cpu09.vhd) CPU core
|
-- (tx_unit3.vhd)
|
-- mon_rom (../spartan3/sys09bug_3se_rom2k_b16.vhd) Monitor ROM
|
|
-- acia6850 (../vhdl/acia6850.vhd) ACIA
|
|
-- ACIA_Clock (../vhdl/ACIA_Clock.vhd) ACIA Baud Clock Divider
|
|
-- keyboard (../vhdl/keyboard.vhd) PS/2 Keyboard Interface
|
|
-- vdu8 (../vhdl/vdu8.vhd) 80 x 25 Video Display
|
|
-- timer (../vhdl/timer.vhd) Timer component
|
|
-- pia_timer (../vhdl/pia_timer.vhd) PIA interrupt Timer cmponent
|
|
-- trap (../vhdl/trap.vhd) Hardware Breakpoint Bus Trap
|
|
-- vdu8 (../vhdl/vdu8.vhd) VDU
|
--
|
--
|
-- Author : John E. Kent
|
-- Author : John E. Kent
|
-- dilbert57@opencores.org
|
-- dilbert57@opencores.org
|
|
-- Memory Map :
|
|
--
|
|
-- $0000 - $7FFF System Block RAM
|
|
-- $E000 - ACIA (SWTPc)
|
|
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
|
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-- $E020 - Keyboard
|
|
-- $E030 - VDU
|
|
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
|
|
-- $E050 - Timer
|
|
-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
|
|
-- $E070 - PIA Single Step Timer (was Reserved for Trace Buffer)
|
|
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
|
|
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
|
|
-- $E0A0 - reserved for SPP Printer Port
|
|
-- $E0B0 - Reserved
|
|
-- $E0C0 - Reserved
|
|
-- $E100 - $E13F Reserved IDE / Compact Flash Card
|
|
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
|
|
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
|
|
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
|
|
-- $E200 - $EFFF Dual Port RAM interface
|
|
-- $F000 - $F7FF Reserved SWTPc DMAF-2
|
|
-- $F800 - $FFFF Sys09bug ROM (Read only)
|
|
-- $FFF0 - $FFFF Reserved for DAT - Dynamic Address Translation (Write Only)
|
|
--
|
|
-- Copyright (C) 2003 - 2010 John Kent
|
|
--
|
|
-- This program is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- This program is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
--
|
--
|
--===========================================================================----
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
--
|
|
--===========================================================================
|
--
|
--
|
-- Revision History:
|
-- Revision History:
|
--===========================================================================--
|
--
|
|
--===========================================================================
|
-- Version 0.1 - 20 March 2003
|
-- Version 0.1 - 20 March 2003
|
-- Version 0.2 - 30 March 2003
|
-- Version 0.2 - 30 March 2003
|
-- Version 0.3 - 29 April 2003
|
-- Version 0.3 - 29 April 2003
|
-- Version 0.4 - 29 June 2003
|
-- Version 0.4 - 29 June 2003
|
--
|
--
|
| Line 81... |
Line 129... |
-- $E040 - Compact Flash (not implemented)
|
-- $E040 - Compact Flash (not implemented)
|
-- $E050 - Timer
|
-- $E050 - Timer
|
-- $E060 - Bus trap
|
-- $E060 - Bus trap
|
-- $E070 - Parallel I/O
|
-- $E070 - Parallel I/O
|
--
|
--
|
|
-- Version 4.1 - July / september 2010
|
|
-- Updated VDU interface
|
|
-- and possible other changes.
|
|
--
|
|
-- Version 4.2 - 14th September 2010
|
|
-- Replaced ACIA_6850 with acia6850
|
|
-- Cleaned up decoding
|
|
-- Added Flasher component
|
|
-- Added Clock Divider component
|
|
--
|
--===========================================================================--
|
--===========================================================================--
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| Line 129... |
Line 187... |
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
-- Clocks
|
|
signal sys_clk : std_logic;
|
|
signal vga_clk : std_logic;
|
|
|
-- BOOT ROM
|
-- BOOT ROM
|
signal rom_cs : Std_logic;
|
signal rom_cs : Std_logic;
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
-- UART Interface signals
|
-- UART Interface signals
|
signal uart_data_out : Std_Logic_Vector(7 downto 0);
|
signal uart_data_out : Std_Logic_Vector(7 downto 0);
|
signal uart_cs : Std_Logic;
|
signal uart_cs : Std_Logic;
|
signal uart_irq : Std_Logic;
|
signal uart_irq : Std_Logic;
|
signal uart_clk : Std_Logic;
|
signal uart_clk : Std_Logic;
|
signal rxbit : Std_Logic;
|
|
signal txbit : Std_Logic;
|
|
signal DCD_n : Std_Logic;
|
|
signal RTS_n : Std_Logic;
|
|
signal CTS_n : Std_Logic;
|
|
|
|
-- timer
|
-- timer
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_cs : std_logic;
|
signal timer_cs : std_logic;
|
signal timer_irq : std_logic;
|
signal timer_irq : std_logic;
|
| Line 161... |
Line 218... |
signal pia_cs : Std_Logic;
|
signal pia_cs : Std_Logic;
|
signal pia_irq_a : Std_Logic;
|
signal pia_irq_a : Std_Logic;
|
signal pia_irq_b : Std_Logic;
|
signal pia_irq_b : Std_Logic;
|
|
|
-- keyboard port
|
-- keyboard port
|
signal keyboard_data_out : std_logic_vector(7 downto 0);
|
signal kbd_data_out : std_logic_vector(7 downto 0);
|
signal keyboard_cs : std_logic;
|
signal kbd_cs : std_logic;
|
signal keyboard_irq : std_logic;
|
signal kbd_irq : std_logic;
|
|
|
-- Video Display Unit
|
-- Video Display Unit
|
signal vga_clk : std_logic;
|
|
signal vdu_cs : std_logic;
|
signal vdu_cs : std_logic;
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
|
|
-- CPU Interface signals
|
-- CPU Interface signals
|
signal cpu_reset : Std_Logic;
|
signal cpu_rst : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_rw : std_logic;
|
signal cpu_rw : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_hold : std_logic;
|
signal cpu_hold : std_logic;
|
| Line 188... |
Line 244... |
signal cpu_nmi : std_logic;
|
signal cpu_nmi : std_logic;
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_out : std_logic_vector(7 downto 0);
|
signal cpu_data_out : std_logic_vector(7 downto 0);
|
|
|
-- CLK_50MHZ clock divide by 2
|
-----------------------------------------------------------------
|
signal clock_div : std_logic_vector(1 downto 0);
|
--
|
signal SysClk : std_logic;
|
-- Clock generator
|
signal Reset_n : std_logic;
|
--
|
signal CountL : std_logic_vector(23 downto 0);
|
-----------------------------------------------------------------
|
|
|
|
component clock_div
|
|
port(
|
|
clk_in : in std_Logic; -- System Clock input
|
|
sys_clk : out std_logic; -- System Clock Out (1/1)
|
|
vga_clk : out std_logic; -- VGA Pixel Clock Out (1/2)
|
|
cpu_clk : out std_logic -- CPU Clock Out (1/4)
|
|
);
|
|
end component;
|
|
|
|
-----------------------------------------------------------------
|
|
--
|
|
-- LED Flasher
|
|
--
|
|
-----------------------------------------------------------------
|
|
|
|
component flasher
|
|
port (
|
|
clk : in std_logic; -- Clock input
|
|
rst : in std_logic; -- Reset input (active high)
|
|
LED : out Std_Logic -- LED output
|
|
);
|
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- CPU09 CPU core
|
-- CPU09 CPU core
|
--
|
--
|
| Line 204... |
Line 283... |
|
|
component cpu09
|
component cpu09
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
rw : out std_logic;
|
|
vma : out std_logic;
|
vma : out std_logic;
|
address : out std_logic_vector(15 downto 0);
|
addr : out std_logic_vector(15 downto 0);
|
|
rw : out std_logic;
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
irq : in std_logic;
|
irq : in std_logic;
|
nmi : in std_logic;
|
nmi : in std_logic;
|
firq : in std_logic;
|
firq : in std_logic;
|
| Line 245... |
Line 324... |
component ram_32k
|
component ram_32k
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
|
addr : in std_logic_vector (14 downto 0);
|
addr : in std_logic_vector (14 downto 0);
|
|
rw : in std_logic;
|
data_in : in std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0)
|
data_out : out std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 263... |
Line 342... |
component pia_timer
|
component pia_timer
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
|
addr : in std_logic_vector(1 downto 0);
|
addr : in std_logic_vector(1 downto 0);
|
|
rw : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irqa : out std_logic;
|
irqa : out std_logic;
|
irqb : out std_logic
|
irqb : out std_logic
|
);
|
);
|
| Line 279... |
Line 358... |
--
|
--
|
-- 6850 ACIA/UART
|
-- 6850 ACIA/UART
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_6850
|
component acia6850
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock
|
clk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic; -- miniUART Chip Select
|
cs : in Std_Logic; -- miniUART Chip Select
|
rw : in Std_Logic; -- Read / Not Write
|
rw : in Std_Logic; -- Read / Not Write
|
| Line 326... |
Line 405... |
component timer
|
component timer
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
|
addr : in std_logic;
|
addr : in std_logic;
|
|
rw : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic
|
irq : out std_logic
|
);
|
);
|
end component;
|
end component;
|
| Line 345... |
Line 424... |
component trap
|
component trap
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
|
vma : in std_logic;
|
vma : in std_logic;
|
|
rw : in std_logic;
|
addr : in std_logic_vector(15 downto 0);
|
addr : in std_logic_vector(15 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic
|
irq : out std_logic
|
);
|
);
|
| Line 368... |
Line 447... |
);
|
);
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
|
addr : in std_logic;
|
addr : in std_logic;
|
|
rw : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic;
|
irq : out std_logic;
|
kbd_clk : inout std_logic;
|
kbd_clk : inout std_logic;
|
kbd_data : inout std_logic
|
kbd_data : inout std_logic
|
| Line 417... |
Line 496... |
vga_hsync_o : out std_logic;
|
vga_hsync_o : out std_logic;
|
vga_vsync_o : out std_logic
|
vga_vsync_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
component BUFG
|
|
port (
|
|
i: in std_logic;
|
|
o: out std_logic
|
|
);
|
|
end component;
|
|
|
|
begin
|
begin
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
----------------------------------------
|
|
--
|
|
-- Clock generator
|
|
--
|
|
----------------------------------------
|
|
|
|
my_clock_div: clock_div port map (
|
|
clk_in => CLK_50MHZ, -- Clock input
|
|
sys_clk => sys_clk, -- System Clock Out (1/1)
|
|
vga_clk => vga_clk, -- CPU/VGA Pixel Clock Out (1/2)
|
|
cpu_clk => open -- (1/4)
|
|
);
|
|
|
|
-----------------------------------------
|
|
--
|
|
-- LED Flasher
|
|
--
|
|
-----------------------------------------
|
|
|
|
my_LED_flasher : flasher port map (
|
|
clk => cpu_clk,
|
|
rst => cpu_rst,
|
|
LED => LED(0)
|
|
);
|
|
|
|
----------------------------------------
|
|
--
|
|
-- 6809 compatible CPU
|
|
--
|
|
----------------------------------------
|
|
|
my_cpu : cpu09 port map (
|
my_cpu : cpu09 port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
rw => cpu_rw,
|
|
vma => cpu_vma,
|
vma => cpu_vma,
|
address => cpu_addr(15 downto 0),
|
addr => cpu_addr(15 downto 0),
|
|
rw => cpu_rw,
|
data_out => cpu_data_out,
|
data_out => cpu_data_out,
|
data_in => cpu_data_in,
|
data_in => cpu_data_in,
|
irq => cpu_irq,
|
irq => cpu_irq,
|
nmi => cpu_nmi,
|
nmi => cpu_nmi,
|
firq => cpu_firq,
|
firq => cpu_firq,
|
| Line 447... |
Line 550... |
hold => cpu_hold
|
hold => cpu_hold
|
);
|
);
|
|
|
my_rom : mon_rom port map (
|
my_rom : mon_rom port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => rom_cs,
|
cs => rom_cs,
|
rw => '1',
|
|
addr => cpu_addr(10 downto 0),
|
addr => cpu_addr(10 downto 0),
|
|
rw => '1',
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => rom_data_out
|
data_out => rom_data_out
|
);
|
);
|
|
|
my_ram : ram_32k port map (
|
my_ram : ram_32k port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => ram_cs,
|
cs => ram_cs,
|
rw => cpu_rw,
|
|
addr => cpu_addr(14 downto 0),
|
addr => cpu_addr(14 downto 0),
|
|
rw => cpu_rw,
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => ram_data_out
|
data_out => ram_data_out
|
);
|
);
|
|
|
my_pia : pia_timer port map (
|
my_pia : pia_timer port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => pia_cs,
|
cs => pia_cs,
|
rw => cpu_rw,
|
|
addr => cpu_addr(1 downto 0),
|
addr => cpu_addr(1 downto 0),
|
|
rw => cpu_rw,
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => pia_data_out,
|
data_out => pia_data_out,
|
irqa => pia_irq_a,
|
irqa => pia_irq_a,
|
irqb => pia_irq_b
|
irqb => pia_irq_b
|
);
|
);
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- ACIA/UART Serial interface
|
-- ACIA/UART Serial interface
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_ACIA : ACIA_6850 port map (
|
my_ACIA : acia6850 port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => uart_cs,
|
cs => uart_cs,
|
rw => cpu_rw,
|
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
|
rw => cpu_rw,
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => uart_data_out,
|
data_out => uart_data_out,
|
irq => uart_irq,
|
irq => uart_irq,
|
RxC => uart_clk,
|
RxC => uart_clk,
|
TxC => uart_clk,
|
TxC => uart_clk,
|
RxD => rxbit,
|
RxD => RS232_DCE_RXD,
|
TxD => txbit,
|
TxD => RS232_DCE_TXD,
|
DCD_n => dcd_n,
|
DCD_n => '0',
|
CTS_n => cts_n,
|
CTS_n => '0',
|
RTS_n => rts_n
|
RTS_n => open
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- ACIA Clock
|
-- ACIA Clock
|
| Line 512... |
Line 614... |
generic map(
|
generic map(
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => SysClk,
|
clk => sys_clk,
|
acia_clk => uart_clk
|
acia_clk => uart_clk
|
);
|
);
|
|
|
|
|
|
|
| Line 529... |
Line 631... |
generic map (
|
generic map (
|
KBD_CLK_FREQ => CPU_CLK_FREQ
|
KBD_CLK_FREQ => CPU_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => keyboard_cs,
|
cs => kbd_cs,
|
rw => cpu_rw,
|
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
|
rw => cpu_rw,
|
data_in => cpu_data_out(7 downto 0),
|
data_in => cpu_data_out(7 downto 0),
|
data_out => keyboard_data_out(7 downto 0),
|
data_out => kbd_data_out(7 downto 0),
|
irq => keyboard_irq,
|
irq => kbd_irq,
|
kbd_clk => PS2_CLK,
|
kbd_clk => PS2_CLK,
|
kbd_data => PS2_DATA
|
kbd_data => PS2_DATA
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
| Line 557... |
Line 659... |
VGA_HOR_BACK_PORCH => 48, -- PIXELS
|
VGA_HOR_BACK_PORCH => 48, -- PIXELS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_VER_CHAR_LINES => 16, -- LINES
|
VGA_VER_CHAR_LINES => 16, -- LINES
|
VGA_VER_FRONT_PORCH => 10, -- LINES
|
VGA_VER_FRONT_PORCH => 10, -- LINES
|
VGA_VER_SYNC => 2, -- LINES
|
VGA_VER_SYNC => 2, -- LINES
|
VGA_VER_FRONT_PORCH => 34 -- LINES
|
VGA_VER_BACK_PORCH => 34 -- LINES
|
)
|
)
|
port map(
|
port map(
|
|
|
-- Control Registers
|
-- Control Registers
|
vdu_clk => cpu_clk, -- 25 MHz System Clock in
|
vdu_clk => cpu_clk, -- 25 MHz System Clock in
|
vdu_rst => cpu_reset,
|
vdu_rst => cpu_rst,
|
vdu_cs => vdu_cs,
|
vdu_cs => vdu_cs,
|
vdu_rw => cpu_rw,
|
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_addr => cpu_addr(2 downto 0),
|
|
vdu_rw => cpu_rw,
|
vdu_data_in => cpu_data_out,
|
vdu_data_in => cpu_data_out,
|
vdu_data_out => vdu_data_out,
|
vdu_data_out => vdu_data_out,
|
|
|
-- vga port connections
|
-- vga port connections
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
| Line 587... |
Line 689... |
-- Timer Module
|
-- Timer Module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_timer : timer port map (
|
my_timer : timer port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => timer_cs,
|
cs => timer_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => timer_data_out,
|
data_out => timer_data_out,
|
| Line 603... |
Line 705... |
-- Bus Trap Interrupt logic
|
-- Bus Trap Interrupt logic
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_trap : trap port map (
|
my_trap : trap port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_rst,
|
cs => trap_cs,
|
cs => trap_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
addr => cpu_addr,
|
addr => cpu_addr,
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => trap_data_out,
|
data_out => trap_data_out,
|
irq => trap_irq
|
irq => trap_irq
|
);
|
);
|
|
|
--
|
|
-- 25 MHz CPU clock
|
|
--
|
|
cpu_clk_buffer : BUFG port map(
|
|
i => clock_div(0),
|
|
o => cpu_clk
|
|
);
|
|
|
|
--
|
|
-- 25 MHz VGA Pixel clock
|
|
--
|
|
vga_clk_buffer : BUFG port map(
|
|
i => clock_div(0),
|
|
o => vga_clk
|
|
);
|
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
mem_decode: process( cpu_clk, Reset_n,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
cpu_addr, cpu_rw, cpu_vma,
|
|
rom_data_out,
|
rom_data_out,
|
ram_data_out,
|
ram_data_out,
|
timer_data_out,
|
timer_data_out,
|
trap_data_out,
|
trap_data_out,
|
pia_data_out,
|
pia_data_out,
|
uart_data_out,
|
uart_data_out,
|
keyboard_data_out,
|
kbd_data_out,
|
vdu_data_out )
|
vdu_data_out )
|
variable decode_addr : std_logic_vector(3 downto 0);
|
|
begin
|
begin
|
-- decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
|
|
decode_addr := cpu_addr(15 downto 12);
|
|
|
|
case decode_addr is
|
rom_cs <= '0';
|
--
|
|
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
|
|
--
|
|
when "1111" => -- $F000 - $FFFF
|
|
cpu_data_in <= rom_data_out;
|
|
rom_cs <= cpu_vma; -- read ROM
|
|
ram_cs <= '0';
|
ram_cs <= '0';
|
uart_cs <= '0';
|
uart_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pia_cs <= '0';
|
pia_cs <= '0';
|
keyboard_cs <= '0';
|
kbd_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
|
|
|
case cpu_addr(15 downto 12) is
|
|
--
|
|
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
|
|
--
|
|
when "1111" => -- $F000 - $FFFF
|
|
cpu_data_in <= rom_data_out;
|
|
rom_cs <= cpu_vma; -- read ROM
|
|
|
--
|
--
|
-- IO Devices $E000 - $EFFF
|
-- IO Devices $E000 - $EFFF
|
--
|
--
|
when "1110" => -- $E000 - $E7FF
|
when "1110" => -- $E000 - $E7FF
|
rom_cs <= '0';
|
|
ram_cs <= '0';
|
|
case cpu_addr(7 downto 4) is
|
case cpu_addr(7 downto 4) is
|
--
|
--
|
-- UART / ACIA $E000
|
-- UART / ACIA $E000
|
--
|
--
|
when "0000" => -- $E000
|
when "0000" => -- $E000
|
cpu_data_in <= uart_data_out;
|
cpu_data_in <= uart_data_out;
|
uart_cs <= cpu_vma;
|
uart_cs <= cpu_vma;
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
|
|
--
|
--
|
-- WD1771 FDC sites at $E010-$E01F
|
-- WD1771 FDC sites at $E010-$E01F
|
--
|
--
|
when "0001" => -- $E010
|
when "0001" => -- $E010
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
|
|
--
|
--
|
-- Keyboard port $E020 - $E02F
|
-- Keyboard port $E020 - $E02F
|
--
|
--
|
when "0010" => -- $E020
|
when "0010" => -- $E020
|
cpu_data_in <= keyboard_data_out;
|
cpu_data_in <= kbd_data_out;
|
uart_cs <= '0';
|
kbd_cs <= cpu_vma;
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= cpu_vma;
|
|
vdu_cs <= '0';
|
|
|
|
--
|
--
|
-- VDU port $E030 - $E03F
|
-- VDU port $E030 - $E03F
|
--
|
--
|
when "0011" => -- $E030
|
when "0011" => -- $E030
|
cpu_data_in <= vdu_data_out;
|
cpu_data_in <= vdu_data_out;
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= cpu_vma;
|
vdu_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Compact Flash $E040 - $E04F
|
-- Compact Flash $E040 - $E04F
|
--
|
--
|
when "0100" => -- $E040
|
when "0100" => -- $E040
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
|
|
--
|
--
|
-- Timer $E050 - $E05F
|
-- Timer $E050 - $E05F
|
--
|
--
|
when "0101" => -- $E050
|
when "0101" => -- $E050
|
cpu_data_in <= timer_data_out;
|
cpu_data_in <= timer_data_out;
|
uart_cs <= '0';
|
|
timer_cs <= cpu_vma;
|
timer_cs <= cpu_vma;
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
|
|
--
|
--
|
-- Bus Trap Logic $E060 - $E06F
|
-- Bus Trap Logic $E060 - $E06F
|
--
|
--
|
when "0110" => -- $E060
|
when "0110" => -- $E060
|
cpu_data_in <= trap_data_out;
|
cpu_data_in <= trap_data_out;
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= cpu_vma;
|
trap_cs <= cpu_vma;
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
|
|
--
|
--
|
-- I/O port $E070 - $E07F
|
-- PIA Timer $E070 - $E07F
|
--
|
--
|
when "0111" => -- $E070
|
when "0111" => -- $E070
|
cpu_data_in <= pia_data_out;
|
cpu_data_in <= pia_data_out;
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= cpu_vma;
|
pia_cs <= cpu_vma;
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
|
|
when others => -- $E080 to $E7FF
|
when others => -- $E080 to $E7FF
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
end case;
|
end case;
|
|
|
--
|
--
|
-- $8000 to $DFFF = null
|
-- $8000 to $DFFF = null
|
--
|
--
|
when "1101" | "1100" | "1011" | "1010" |
|
when "1101" | "1100" | "1011" | "1010" |
|
"1001" | "1000" =>
|
"1001" | "1000" =>
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
rom_cs <= '0';
|
|
ram_cs <= '0';
|
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
--
|
--
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
when others =>
|
when others =>
|
cpu_data_in <= ram_data_out;
|
cpu_data_in <= ram_data_out;
|
rom_cs <= '0';
|
|
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
uart_cs <= '0';
|
|
timer_cs <= '0';
|
|
trap_cs <= '0';
|
|
pia_cs <= '0';
|
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Assign CPU clock, reset, interrupt, halt & hold signals
|
|
-- as well as LED signals
|
--
|
--
|
interrupts : process( Reset_n,
|
assign_signals : process( vga_clk, BTN_SOUTH,
|
pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq
|
pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, kbd_irq
|
)
|
)
|
begin
|
begin
|
cpu_reset <= not Reset_n; -- CPU reset is active high
|
cpu_clk <= vga_clk;
|
cpu_irq <= uart_irq or keyboard_irq;
|
cpu_rst <= BTN_SOUTH; -- CPU reset is active high
|
|
cpu_irq <= uart_irq or kbd_irq;
|
cpu_nmi <= pia_irq_a or trap_irq;
|
cpu_nmi <= pia_irq_a or trap_irq;
|
cpu_firq <= pia_irq_b or timer_irq;
|
cpu_firq <= pia_irq_b or timer_irq;
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= '0';
|
cpu_hold <= '0';
|
end process;
|
|
|
|
--
|
-- LED outputs
|
--
|
LED(7 downto 1) <= (others=>'1');
|
my_led_flasher: process( SysClk, Reset_n, CountL )
|
|
begin
|
|
if Reset_n = '0' then
|
|
CountL <= "000000000000000000000000";
|
|
elsif(SysClk'event and SysClk = '0') then
|
|
CountL <= CountL + 1;
|
|
end if;
|
|
LED(7 downto 0) <= CountL(23 downto 16);
|
|
end process;
|
|
|
|
--
|
|
-- Clock divider
|
|
--
|
|
my_clock_divider: process( SysClk )
|
|
begin
|
|
if SysClk'event and SysClk='0' then
|
|
clock_div <= clock_div + "01";
|
|
end if;
|
|
end process;
|
end process;
|
|
|
DCD_n <= '0';
|
|
CTS_n <= '0';
|
|
Reset_n <= not BTN_SOUTH; -- CPU reset is active high
|
|
SysClk <= CLK_50MHZ;
|
|
rxbit <= RS232_DCE_RXD;
|
|
RS232_DCE_TXD <= txbit;
|
|
|
|
end my_computer; --===================== End of architecture =======================--
|
end my_computer; --===================== End of architecture =======================--
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
