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-- $Id: System09_Digilent_3S500E.vhd,v 1.3 2008-03-14 15:52:44 dilbert57 Exp $
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-- $Id: System09_Digilent_3S500E.vhd,v 1.4 2008-08-20 06:00:55 davidgb Exp $
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--===========================================================================----
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--===========================================================================----
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--
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--
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-- S Y N T H E Z I A B L E System09 - SOC.
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-- S Y N T H E Z I A B L E System09 - SOC.
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--
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--
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity My_System09 is
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entity my_system09 is
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port(
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port(
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CLK_50MHZ : in Std_Logic; -- System Clock input
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CLK_50MHZ : in Std_Logic; -- System Clock input
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BTN_SOUTH : in Std_Logic;
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BTN_SOUTH : in Std_Logic;
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-- PS/2 Keyboard
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-- PS/2 Keyboard
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RS232_DCE_TXD : out std_logic;
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RS232_DCE_TXD : out std_logic;
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-- LEDS & Switches
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-- LEDS & Switches
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LED : out std_logic_vector(7 downto 0)
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LED : out std_logic_vector(7 downto 0)
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);
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);
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end My_System09;
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end my_system09;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for System09
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-- Architecture for System09
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture my_computer of My_System09 is
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architecture my_computer of my_system09 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
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constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
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constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
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constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic;
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addr : in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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irq : out std_logic;
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irq : out std_logic
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timer_in : in std_logic;
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-- ;
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timer_out : out std_logic
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-- timer_in : in std_logic;
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-- timer_out : out std_logic
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);
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);
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end component;
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end component;
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------------------------------------------------------------
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------------------------------------------------------------
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--
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--
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cs => timer_cs,
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cs => timer_cs,
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rw => cpu_rw,
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rw => cpu_rw,
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addr => cpu_addr(0),
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addr => cpu_addr(0),
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data_in => cpu_data_out,
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data_in => cpu_data_out,
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data_out => timer_data_out,
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data_out => timer_data_out,
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irq => timer_irq,
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irq => timer_irq
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timer_in => CountL(5)
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-- ,
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-- timer_in => CountL(5)
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-- timer_out => timer_out
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-- timer_out => timer_out
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);
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);
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----------------------------------------
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----------------------------------------
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--
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--
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