| Line 26... |
Line 26... |
--
|
--
|
-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
|
-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
|
-- cpu09 (cpu09.vhd) CPU core
|
-- cpu09 (cpu09.vhd) CPU core
|
-- ACIA_6850 (acia6850.vhd) ACIA / UART
|
-- ACIA_6850 (acia6850.vhd) ACIA / UART
|
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
|
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
|
-- keyboard (keyboard.vhd) PS/2 Keyboard interface
|
|
-- (ps2_keyboard.vhd)
|
|
-- (keymap_rom_slice.vhd) Key map table
|
|
-- vdu8_mono (vdu8_mono.vhd) Monochrome VDU
|
|
-- (char_rom2k_b16.vhd)
|
|
-- (ram2k_b16.vhd)
|
|
-- timer (timer.vhd) Interrupt timer
|
-- timer (timer.vhd) Interrupt timer
|
-- trap (trap.vhd) Bus condition trap logic
|
-- trap (trap.vhd) Bus condition trap logic
|
-- flex_ram (flex9_ram8k_b16.vhd) Flex operating system
|
-- flex_ram (flex9_ram8k_b16.vhd) Flex operating system
|
-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM
|
-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM
|
--
|
--
|
| Line 47... |
Line 41... |
--
|
--
|
-- $0000 - User program RAM (32K Bytes)
|
-- $0000 - User program RAM (32K Bytes)
|
-- $C000 - Flex Operating System memory (8K Bytes)
|
-- $C000 - Flex Operating System memory (8K Bytes)
|
-- $E000 - ACIA (SWTPc)
|
-- $E000 - ACIA (SWTPc)
|
-- $E010 - Reserved for FD1771 FDC (SWTPc)
|
-- $E010 - Reserved for FD1771 FDC (SWTPc)
|
-- $E020 - Keyboard
|
|
-- $E030 - VDU
|
|
-- $E040 - IDE / Compact Flash interface
|
|
-- $E050 - Timer
|
-- $E050 - Timer
|
-- $E060 - Bus trap
|
-- $E060 - Bus trap
|
-- $E070 - Reserced for Parallel I/O (B5-X300)
|
-- $E070 - Reserced for Parallel I/O (B5-X300)
|
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
|
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
|
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
|
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
|
| Line 136... |
Line 127... |
use unisim.vcomponents.all;
|
use unisim.vcomponents.all;
|
|
|
entity system09 is
|
entity system09 is
|
port(
|
port(
|
CLKA : in Std_Logic; -- 100MHz Clock input
|
CLKA : in Std_Logic; -- 100MHz Clock input
|
-- CLKB : in Std_Logic; -- 50MHz Clock input
|
|
SW2_N : in Std_logic; -- Master Reset input (active low)
|
SW2_N : in Std_logic; -- Master Reset input (active low)
|
SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
|
SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
|
|
|
|
|
|
|
-- RS232 Port
|
-- RS232 Port
|
RS232_RXD : in Std_Logic;
|
RS232_RXD : in Std_Logic;
|
RS232_TXD : out Std_Logic;
|
RS232_TXD : out Std_Logic;
|
|
|
|
|
-- Status 7 segment LED
|
-- Status 7 segment LED
|
S : out std_logic_vector(7 downto 0)
|
S : out std_logic_vector(7 downto 0)
|
|
|
|
|
-- CPU Debug Interface signals
|
-- CPU Debug Interface signals
|
-- cpu_reset_o : out Std_Logic;
|
-- cpu_reset_o : out Std_Logic;
|
-- cpu_clk_o : out Std_Logic;
|
-- cpu_clk_o : out Std_Logic;
|
-- cpu_rw_o : out std_logic;
|
-- cpu_rw_o : out std_logic;
|
-- cpu_vma_o : out std_logic;
|
-- cpu_vma_o : out std_logic;
|
| Line 192... |
Line 178... |
constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width
|
constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width
|
|
|
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock
|
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock
|
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
|
|
constant VGA_CLK_DIV : natural := ((MEM_CLK_FREQ*1000)/VGA_CLK_FREQ);
|
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
constant TRESET : natural := 300; -- min initialization interval (us)
|
constant TRESET : natural := 300; -- min initialization interval (us)
|
constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval
|
constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval
|
| Line 224... |
Line 208... |
signal txd : Std_Logic;
|
signal txd : Std_Logic;
|
signal DCD_n : Std_Logic;
|
signal DCD_n : Std_Logic;
|
signal RTS_n : Std_Logic;
|
signal RTS_n : Std_Logic;
|
signal CTS_n : Std_Logic;
|
signal CTS_n : Std_Logic;
|
|
|
-- keyboard port
|
|
signal keyboard_data_out : std_logic_vector(7 downto 0);
|
|
signal keyboard_cs : std_logic;
|
|
signal keyboard_irq : std_logic;
|
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_cs : std_logic; -- memory chip select
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram_data_out : std_logic_vector(7 downto 0);
|
signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
|
signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
|
signal ram_wr_req : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge)
|
signal ram_wr_req : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge)
|
| Line 255... |
Line 234... |
|
|
-- Dynamic Address Translation
|
-- Dynamic Address Translation
|
signal dat_cs : std_logic;
|
signal dat_cs : std_logic;
|
signal dat_addr : std_logic_vector(7 downto 0);
|
signal dat_addr : std_logic_vector(7 downto 0);
|
|
|
-- Video Display Unit
|
|
signal vdu_cs : std_logic;
|
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
|
signal vga_red_o : std_logic;
|
|
signal vga_green_o : std_logic;
|
|
signal vga_blue_o : std_logic;
|
|
|
|
-- timer
|
-- timer
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_cs : std_logic;
|
signal timer_cs : std_logic;
|
signal timer_irq : std_logic;
|
signal timer_irq : std_logic;
|
|
|
| Line 286... |
Line 258... |
signal pb_count : std_logic_vector(3 downto 0); -- hold counter
|
signal pb_count : std_logic_vector(3 downto 0); -- hold counter
|
signal pb_hold_state : hold_state_type;
|
signal pb_hold_state : hold_state_type;
|
signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register
|
signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register
|
signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register
|
signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register
|
|
|
-- Peripheral chip selects on Peripheral Bus
|
|
signal ide_cs : std_logic; -- IDE CF interface
|
|
signal ether_cs : std_logic; -- Ethernet interface
|
|
signal slot1_cs : std_logic; -- Expansion slot 1
|
|
signal slot2_cs : std_logic; -- Expansion slot 2
|
|
|
|
signal rst_i : std_logic; -- internal reset signal
|
signal rst_i : std_logic; -- internal reset signal
|
signal clk_i : std_logic; -- internal master clock signal
|
signal clk_i : std_logic; -- internal master clock signal
|
signal lock : std_logic; -- SDRAM clock DLL lock indicator
|
|
|
|
-- signals that go through the SDRAM host-side interface
|
-- signals that go through the SDRAM host-side interface
|
signal opBegun : std_logic; -- SDRAM operation started indicator
|
signal opBegun : std_logic; -- SDRAM operation started indicator
|
signal earlyBegun : std_logic; -- SDRAM operation started indicator
|
signal earlyBegun : std_logic; -- SDRAM operation started indicator
|
signal ramDone : std_logic; -- SDRAM operation complete indicator
|
signal ramDone : std_logic; -- SDRAM operation complete indicator
|
| Line 319... |
Line 284... |
signal ram_state : ram_type;
|
signal ram_state : ram_type;
|
|
|
signal flash_ce_n : std_logic;
|
signal flash_ce_n : std_logic;
|
signal rs232_cts : Std_Logic;
|
signal rs232_cts : Std_Logic;
|
signal rs232_rts : Std_Logic;
|
signal rs232_rts : Std_Logic;
|
signal ether_cs_n : std_logic;
|
|
signal ether_aen : std_logic;
|
|
signal ether_bhe_n : std_logic;
|
|
signal slot1_cs_n : std_logic;
|
|
signal slot2_cs_n : std_logic;
|
|
|
|
-- signal BaudCount : std_logic_vector(5 downto 0);
|
-- signal BaudCount : std_logic_vector(5 downto 0);
|
|
|
signal CountL : std_logic_vector(23 downto 0);
|
signal CountL : std_logic_vector(23 downto 0);
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal Clk25 : std_logic;
|
signal Clk25 : std_logic;
|
|
|
signal vga_clk : std_logic;
|
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- CPU09 CPU core
|
-- CPU09 CPU core
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
| Line 437... |
Line 395... |
clk : in Std_Logic; -- System Clock Input
|
clk : in Std_Logic; -- System Clock Input
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer module
|
-- Timer module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
| Line 583... |
Line 538... |
port map(
|
port map(
|
clk => Clk_i,
|
clk => Clk_i,
|
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer Module
|
-- Timer Module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
| Line 631... |
Line 585... |
addr_lo => cpu_addr(3 downto 0),
|
addr_lo => cpu_addr(3 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => dat_addr(7 downto 0)
|
data_out => dat_addr(7 downto 0)
|
);
|
);
|
|
|
|
|
cpu_clk_buffer : BUFG
|
cpu_clk_buffer : BUFG
|
port map(
|
port map(
|
i => Clk25,
|
i => Clk25,
|
o => cpu_clk
|
o => cpu_clk
|
);
|
);
|
|
|
|
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
| Line 650... |
Line 602... |
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
dat_addr,
|
dat_addr,
|
rom_data_out,
|
rom_data_out,
|
flex_data_out,
|
flex_data_out,
|
acia_data_out,
|
acia_data_out,
|
keyboard_data_out,
|
|
vdu_data_out,
|
|
pb_data_out,
|
pb_data_out,
|
timer_data_out,
|
timer_data_out,
|
trap_data_out,
|
trap_data_out,
|
ram_data_out
|
ram_data_out
|
)
|
)
|
| Line 663... |
Line 613... |
cpu_data_in <= (others=>'0');
|
cpu_data_in <= (others=>'0');
|
dat_cs <= '0';
|
dat_cs <= '0';
|
rom_cs <= '0';
|
rom_cs <= '0';
|
flex_cs <= '0';
|
flex_cs <= '0';
|
acia_cs <= '0';
|
acia_cs <= '0';
|
keyboard_cs <= '0';
|
|
vdu_cs <= '0';
|
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pb_cs <= '0';
|
pb_cs <= '0';
|
ide_cs <= '0';
|
|
ether_cs <= '0';
|
|
slot1_cs <= '0';
|
|
slot2_cs <= '0';
|
|
ram_cs <= '0';
|
ram_cs <= '0';
|
|
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
dat_cs <= cpu_vma; -- write DAT
|
dat_cs <= cpu_vma; -- write DAT
|
| Line 709... |
Line 653... |
-- Reserved
|
-- Reserved
|
-- Floppy Disk Controller port $E010 - $E01F
|
-- Floppy Disk Controller port $E010 - $E01F
|
--
|
--
|
|
|
--
|
--
|
-- Keyboard port $E020 - $E02F
|
|
--
|
|
when "0010" => -- $E020
|
|
cpu_data_in <= keyboard_data_out;
|
|
keyboard_cs <= cpu_vma;
|
|
|
|
--
|
|
-- VDU port $E030 - $E03F
|
|
--
|
|
when "0011" => -- $E030
|
|
cpu_data_in <= vdu_data_out;
|
|
vdu_cs <= cpu_vma;
|
|
|
|
--
|
|
-- Reserved SWTPc MP-T Timer $E040 - $E04F
|
-- Reserved SWTPc MP-T Timer $E040 - $E04F
|
--
|
--
|
when "0100" => -- $E040
|
when "0100" => -- $E040
|
cpu_data_in <= (others=> '0');
|
cpu_data_in <= (others=> '0');
|
|
|
| Line 758... |
Line 688... |
when others => -- $E0A0 to $E0FF
|
when others => -- $E0A0 to $E0FF
|
null;
|
null;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- XST-3.0 Peripheral Bus goes here
|
|
-- $E100 to $E1FF
|
|
-- Four devices
|
|
-- IDE, Ethernet, Slot1, Slot2
|
|
--
|
|
when "0001" =>
|
|
cpu_data_in <= pb_data_out;
|
|
pb_cs <= cpu_vma;
|
|
case cpu_addr(7 downto 6) is
|
|
--
|
|
-- IDE Interface $E100 to $E13F
|
|
--
|
|
when "00" =>
|
|
ide_cs <= cpu_vma;
|
|
--
|
|
-- Ethernet Interface $E140 to $E17F
|
|
--
|
|
when "01" =>
|
|
ether_cs <= cpu_vma;
|
|
--
|
|
-- Slot 1 Interface $E180 to $E1BF
|
|
--
|
|
when "10" =>
|
|
slot1_cs <= cpu_vma;
|
|
--
|
|
-- Slot 2 Interface $E1C0 to $E1FF
|
|
--
|
|
when "11" =>
|
|
slot2_cs <= cpu_vma;
|
|
--
|
|
-- Nothing else
|
|
--
|
|
when others =>
|
|
null;
|
|
end case;
|
|
|
|
--
|
|
-- $E200 to $EFFF reserved for future use
|
-- $E200 to $EFFF reserved for future use
|
--
|
--
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
| Line 818... |
Line 711... |
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
|
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( SW3_N,
|
interrupts : process( SW3_N,
|
pb_cs, pb_hold, pb_release, ram_hold,
|
pb_cs, pb_hold, pb_release, ram_hold,
|
-- ether_irq,
|
|
acia_irq,
|
acia_irq,
|
keyboard_irq,
|
|
trap_irq,
|
trap_irq,
|
timer_irq
|
timer_irq
|
)
|
)
|
begin
|
begin
|
pb_hold <= pb_cs and (not pb_release);
|
pb_hold <= pb_cs and (not pb_release);
|
cpu_irq <= acia_irq or keyboard_irq;
|
cpu_irq <= acia_irq;
|
cpu_nmi <= trap_irq or not( SW3_N );
|
cpu_nmi <= trap_irq or not( SW3_N );
|
cpu_firq <= timer_irq;
|
cpu_firq <= timer_irq;
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= pb_hold or ram_hold;
|
cpu_hold <= pb_hold or ram_hold;
|
FLASH_CE_N <= '1';
|
FLASH_CE_N <= '1';
|
| Line 876... |
Line 765... |
end process;
|
end process;
|
|
|
--
|
--
|
-- Reset button and reset timer
|
-- Reset button and reset timer
|
--
|
--
|
my_switch_assignments : process( rst_i, SW2_N, lock )
|
my_switch_assignments : process( rst_i, SW2_N)
|
begin
|
begin
|
rst_i <= not SW2_N;
|
rst_i <= not SW2_N;
|
cpu_reset <= rst_i or (not lock);
|
cpu_reset <= rst_i;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- RS232 signals:
|
-- RS232 signals:
|
--
|
--
|
| Line 895... |
Line 784... |
RS232_TXD <= txd;
|
RS232_TXD <= txd;
|
RS232_RTS <= rts_n;
|
RS232_RTS <= rts_n;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Pin assignments for ethernet controller
|
|
--
|
|
my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs )
|
|
begin
|
|
ether_cs_n <= not ether_cs;
|
|
ether_aen <= not ether_cs; -- Ethernet address enable not
|
|
ether_bhe_n <= '1'; -- Ethernet bus high enable - 8 bit access only
|
|
end process;
|
|
|
|
--
|
|
-- I/O expansion slot assignments
|
|
--
|
|
my_slot_assignments : process( slot1_cs, slot2_cs)
|
|
begin
|
|
slot1_cs_n <= not slot1_cs;
|
|
slot2_cs_n <= not slot2_cs;
|
|
end process;
|
|
|
|
|
|
--
|
|
-- CPU read data request on rising CPU clock edge
|
-- CPU read data request on rising CPU clock edge
|
--
|
--
|
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
|
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
|
begin
|
begin
|
if hRd = '1' then
|
if hRd = '1' then
|
| Line 942... |
Line 811... |
ram_wr_req <= '1';
|
ram_wr_req <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
status_leds : process( rst_i, cpu_reset, lock )
|
status_leds : process( rst_i, cpu_reset)
|
begin
|
begin
|
S(0) <= rst_i;
|
S(7) <= rst_i;
|
S(1) <= cpu_reset;
|
S(6) <= cpu_reset;
|
S(2) <= lock;
|
S(2) <= countL(23);
|
S(3) <= countL(23);
|
S(3) <= countL(22);
|
S(7 downto 4) <= "0000";
|
S(4) <= countL(21);
|
|
S(5) <= countL(20);
|
|
S(1) <= '1'; -- countL(19);
|
|
S(0) <= '0'; -- countL(18);
|
|
--S(7 downto 4) <= "0000";
|
end process;
|
end process;
|
|
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- cpu_halt, cpu_hold,
|
-- cpu_halt, cpu_hold,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
