| Line 163... |
Line 163... |
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- constants
|
-- constants
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
-- SDRAM
|
|
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz
|
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz
|
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
|
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
|
constant PIPE_EN : boolean := false; -- if true, enable pipelined read operations
|
|
constant MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh
|
|
constant MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank
|
|
constant DATA_WIDTH : natural := 16; -- host & SDRAM data width
|
|
constant NROWS : natural := 8192; -- number of rows in SDRAM array
|
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constant NCOLS : natural := 512; -- number of columns in SDRAM array
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constant HADDR_WIDTH : natural := 24; -- host-side address width
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constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width
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|
|
|
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock
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constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock (in Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
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| Line 209... |
Line 200... |
signal DCD_n : Std_Logic;
|
signal DCD_n : Std_Logic;
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signal RTS_n : Std_Logic;
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signal RTS_n : Std_Logic;
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signal CTS_n : Std_Logic;
|
signal CTS_n : Std_Logic;
|
|
|
-- RAM
|
-- RAM
|
signal ram_cs : std_logic; -- memory chip select
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signal ram_cs : std_logic;
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signal ram_data_out : std_logic_vector(7 downto 0);
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signal ram_data_out : std_logic_vector(7 downto 0);
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signal ram_rd_req : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
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signal ram_wr_req : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge)
|
|
signal ram_hold : std_logic; -- hold off slow accesses
|
|
signal ram_release : std_logic; -- Release ram hold
|
|
|
|
-- CPU Interface signals
|
-- CPU Interface signals
|
signal cpu_reset : Std_Logic;
|
signal cpu_reset : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_rw : std_logic;
|
signal cpu_rw : std_logic;
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| Line 244... |
Line 231... |
-- trap
|
-- trap
|
signal trap_cs : std_logic;
|
signal trap_cs : std_logic;
|
signal trap_data_out : std_logic_vector(7 downto 0);
|
signal trap_data_out : std_logic_vector(7 downto 0);
|
signal trap_irq : std_logic;
|
signal trap_irq : std_logic;
|
|
|
-- Peripheral Bus port
|
|
signal pb_data_out : std_logic_vector(7 downto 0);
|
|
signal pb_cs : std_logic; -- peripheral bus chip select
|
|
signal pb_wru : std_logic; -- upper byte write strobe
|
|
signal pb_wrl : std_logic; -- lower byte write strobe
|
|
signal pb_rdu : std_logic; -- upper byte read strobe
|
|
signal pb_rdl : std_logic; -- lower byte read strobe
|
|
signal pb_hold : std_logic; -- hold peripheral bus access
|
|
signal pb_release : std_logic; -- release hold of peripheral bus
|
|
signal pb_count : std_logic_vector(3 downto 0); -- hold counter
|
|
signal pb_hold_state : hold_state_type;
|
|
signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register
|
|
signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register
|
|
|
|
signal rst_i : std_logic; -- internal reset signal
|
signal rst_i : std_logic; -- internal reset signal
|
signal clk_i : std_logic; -- internal master clock signal
|
signal clk_i : std_logic; -- internal master clock signal
|
|
|
-- signals that go through the SDRAM host-side interface
|
|
signal opBegun : std_logic; -- SDRAM operation started indicator
|
|
signal earlyBegun : std_logic; -- SDRAM operation started indicator
|
|
signal ramDone : std_logic; -- SDRAM operation complete indicator
|
|
signal rdDone : std_logic; -- SDRAM read operation complete indicator
|
|
signal wrDone : std_logic; -- SDRAM write operation complete indicator
|
|
signal hAddr : std_logic_vector(HADDR_WIDTH-1 downto 0); -- host address bus
|
|
signal hDIn : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM
|
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signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM
|
|
signal hRd : std_logic; -- host-side read control signal
|
|
signal hWr : std_logic; -- host-side write control signal
|
|
signal hUds : std_logic; -- host-side upper data strobe
|
|
signal hLds : std_logic; -- host-side lower data strobe
|
|
signal rdPending : std_logic; -- read operation pending in SDRAM pipeline
|
|
type ram_type is (ram_state_0,
|
|
ram_state_rd1, ram_state_rd2,
|
|
ram_state_wr1,
|
|
ram_state_3 );
|
|
signal ram_state : ram_type;
|
|
|
|
signal flash_ce_n : std_logic;
|
|
signal rs232_cts : Std_Logic;
|
signal rs232_cts : Std_Logic;
|
signal rs232_rts : Std_Logic;
|
signal rs232_rts : Std_Logic;
|
|
|
-- signal BaudCount : std_logic_vector(5 downto 0);
|
|
|
|
signal CountL : std_logic_vector(23 downto 0);
|
signal CountL : std_logic_vector(23 downto 0);
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal Clk25 : std_logic;
|
signal Clk25 : std_logic;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
| Line 352... |
Line 302... |
data_out : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
----------------------------------------
|
|
--
|
|
-- 32KBytes Block RAM 0000
|
|
-- $0000 - $7FFF
|
|
--
|
|
----------------------------------------
|
|
|
|
component ram_32k
|
|
Port (
|
|
clk : in std_logic;
|
|
rst : in std_logic;
|
|
cs : in std_logic;
|
|
rw : in std_logic;
|
|
addr : in std_logic_vector (14 downto 0);
|
|
data_out : out std_logic_vector (7 downto 0);
|
|
data_in : in std_logic_vector (7 downto 0)
|
|
);
|
|
end component;
|
|
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- 6850 Compatible ACIA / UART
|
-- 6850 Compatible ACIA / UART
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
| Line 510... |
Line 480... |
addr => cpu_addr(12 downto 0),
|
addr => cpu_addr(12 downto 0),
|
data_out => flex_data_out,
|
data_out => flex_data_out,
|
data_in => cpu_data_out
|
data_in => cpu_data_out
|
);
|
);
|
|
|
|
my_32k : ram_32k
|
|
port map (
|
|
clk => cpu_clk,
|
|
rst => cpu_reset,
|
|
cs => ram_cs,
|
|
rw => cpu_rw,
|
|
addr => cpu_addr(14 downto 0),
|
|
data_out => ram_data_out,
|
|
data_in => cpu_data_out
|
|
);
|
|
|
my_acia : acia6850
|
my_acia : acia6850
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => acia_cs,
|
cs => acia_cs,
|
| Line 603... |
Line 584... |
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
dat_addr,
|
dat_addr,
|
rom_data_out,
|
rom_data_out,
|
flex_data_out,
|
flex_data_out,
|
acia_data_out,
|
acia_data_out,
|
pb_data_out,
|
|
timer_data_out,
|
timer_data_out,
|
trap_data_out,
|
trap_data_out,
|
ram_data_out
|
ram_data_out
|
)
|
)
|
begin
|
begin
|
| Line 616... |
Line 596... |
rom_cs <= '0';
|
rom_cs <= '0';
|
flex_cs <= '0';
|
flex_cs <= '0';
|
acia_cs <= '0';
|
acia_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
pb_cs <= '0';
|
|
ram_cs <= '0';
|
ram_cs <= '0';
|
|
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
dat_cs <= cpu_vma; -- write DAT
|
dat_cs <= cpu_vma; -- write DAT
|
| Line 703... |
Line 682... |
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
cpu_data_in <= flex_data_out;
|
cpu_data_in <= flex_data_out;
|
flex_cs <= cpu_vma;
|
flex_cs <= cpu_vma;
|
|
|
--
|
--
|
|
-- 32k RAM $00000 - $07FFF
|
|
--
|
|
elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
|
|
cpu_data_in <= ram_data_out;
|
|
ram_cs <= cpu_vma;
|
|
|
|
--
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
else
|
else
|
cpu_data_in <= ram_data_out;
|
cpu_data_in <= ram_data_out;
|
ram_cs <= cpu_vma;
|
ram_cs <= cpu_vma;
|
| Line 716... |
Line 702... |
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( SW3_N,
|
interrupts : process( SW3_N,
|
pb_cs, pb_hold, pb_release, ram_hold,
|
|
acia_irq,
|
acia_irq,
|
trap_irq,
|
trap_irq,
|
timer_irq
|
timer_irq
|
)
|
)
|
begin
|
begin
|
pb_hold <= pb_cs and (not pb_release);
|
|
cpu_irq <= acia_irq;
|
cpu_irq <= acia_irq;
|
cpu_nmi <= trap_irq or not( SW3_N );
|
cpu_nmi <= trap_irq or not( SW3_N );
|
cpu_firq <= timer_irq;
|
cpu_firq <= timer_irq;
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= pb_hold or ram_hold;
|
cpu_hold <= '0'; -- pb_hold or ram_hold;
|
FLASH_CE_N <= '1';
|
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Flash 7 segment LEDS
|
-- Flash 7 segment LEDS
|
--
|
--
|
| Line 784... |
Line 767... |
dcd_n <= '0';
|
dcd_n <= '0';
|
RS232_TXD <= txd;
|
RS232_TXD <= txd;
|
RS232_RTS <= rts_n;
|
RS232_RTS <= rts_n;
|
end process;
|
end process;
|
|
|
--
|
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw)
|
-- CPU read data request on rising CPU clock edge
|
|
--
|
|
ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
|
|
begin
|
|
if hRd = '1' then
|
|
ram_rd_req <= '0';
|
|
elsif rising_edge(cpu_clk) then
|
|
if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
|
|
ram_rd_req <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--
|
|
-- CPU write data to RAM valid on rising CPU clock edge
|
|
--
|
|
ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
|
|
begin
|
|
if hWr = '1' then
|
|
ram_wr_req <= '0';
|
|
elsif rising_edge(cpu_clk) then
|
|
if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
|
|
ram_wr_req <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
status_leds : process( rst_i, cpu_reset)
|
|
begin
|
begin
|
S(0) <= cpu_reset;
|
S(0) <= cpu_addr(0);
|
S(1) <= countL(23);
|
S(1) <= cpu_addr(1);
|
S(2) <= RS232_RXD;
|
S(2) <= cpu_addr(2);
|
S(3) <= txd;
|
S(3) <= cpu_addr(3);
|
S(4) <= Clk25;
|
S(4) <= cpu_addr(4);
|
S(5) <= '0';
|
S(5) <= cpu_addr(5);
|
S(6) <= '0';
|
S(6) <= cpu_rw;
|
S(7) <= '0';
|
S(7) <= '0';
|
--S(7 downto 4) <= "0000";
|
--S(7 downto 4) <= "0000";
|
end process;
|
end process;
|
|
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
