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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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entity system09 is
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entity system09 is
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port(
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port(
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CLKA : in Std_Logic; -- 100MHz Clock input
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CLKA : in Std_Logic; -- 100MHz Clock input
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--SW2_N : in Std_logic; -- Master Reset input (active low)
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RESET_N : in Std_logic; -- Master Reset input (active low)
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--SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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-- RS232 Port
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-- RS232 Port
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RS232_RXD : in Std_Logic;
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--RS232_CTS : in std_logic;
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RS232_TXD : out Std_Logic;
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--RS232_RTS : out std_logic;
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RS232_RXD : in Std_Logic; -- RS-232 data in
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-- Status 7 segment LED
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RS232_TXD : out Std_Logic -- RS-232 data out
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sw : in std_logic_vector(7 downto 0);
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btn : in std_logic_vector(4 downto 0);
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S : out std_logic_vector(7 downto 0)
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-- CPU Debug Interface signals
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-- CPU Debug Interface signals
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-- cpu_reset_o : out Std_Logic;
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-- cpu_reset_o : out Std_Logic;
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-- cpu_clk_o : out Std_Logic;
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-- cpu_clk_o : out Std_Logic;
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-- cpu_rw_o : out std_logic;
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-- cpu_rw_o : out std_logic;
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architecture rtl of system09 is
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architecture rtl of system09 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_CLK_FREQ : natural := 100_000_000; -- FPGA System Clock (in Hz)
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constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
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constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock (in Hz)
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constant CPU_CLK_FREQ : natural := 1; --25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
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constant TRESET : natural := 300; -- min initialization interval (us)
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constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal pbtn : std_logic_vector(4 downto 0);
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signal SW3_N : std_logic;
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signal SW2_N : std_logic;
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-- BOOT ROM
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-- BOOT ROM
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signal rom_cs : Std_logic;
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signal rom_cs : Std_logic;
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
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signal rom_data_out : Std_Logic_Vector(7 downto 0);
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-- Flex Memory & Monitor Stack
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-- Flex Memory & Monitor Stack
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signal clk_i : std_logic; -- internal master clock signal
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signal clk_i : std_logic; -- internal master clock signal
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signal rs232_cts : Std_Logic;
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signal rs232_cts : Std_Logic;
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signal rs232_rts : Std_Logic;
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signal rs232_rts : Std_Logic;
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signal CountL : std_logic_vector(23 downto 0);
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal Clk25 : std_logic;
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signal Clk25 : std_logic;
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component btn_debounce
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Port ( BTN_I : in STD_LOGIC_VECTOR (4 downto 0);
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CLK : in STD_LOGIC;
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BTN_O : out STD_LOGIC_VECTOR (4 downto 0));
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end component;
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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-- CPU09 CPU core
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-- CPU09 CPU core
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--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0)
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data_out : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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----------------------------------------
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--
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--
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-- Clock buffer
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-- Clock buffer
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--
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--
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----------------------------------------
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component BUFG
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component BUFG
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Port (
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Port (
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i: in std_logic;
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i: in std_logic;
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o: out std_logic
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o: out std_logic
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);
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);
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end component;
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end component;
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begin
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begin
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clk_i <= CLKA;
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clk_i <= CLKA;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Instantiation of internal components
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-- Instantiation of internal components
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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end process;
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end process;
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--
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--
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-- Interrupts and other bus control signals
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-- Interrupts and other bus control signals
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--
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--
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interrupts : process( SW3_N,
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interrupts : process( NMI_N,
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acia_irq,
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acia_irq,
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trap_irq,
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trap_irq,
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timer_irq
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timer_irq
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)
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)
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begin
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begin
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cpu_irq <= acia_irq;
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cpu_irq <= acia_irq;
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cpu_nmi <= trap_irq or not( SW3_N );
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cpu_nmi <= trap_irq or not( NMI_N );
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cpu_firq <= timer_irq;
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cpu_firq <= timer_irq;
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cpu_halt <= '0';
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cpu_halt <= '0';
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cpu_hold <= '0'; -- pb_hold or ram_hold;
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cpu_hold <= '0'; -- pb_hold or ram_hold;
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end process;
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end process;
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--
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--
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-- Flash 7 segment LEDS
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-- Generate CPU & Pixel Clock from Memory Clock
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--
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--
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my_led_flasher: process( clk_i, rst_i, CountL )
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my_prescaler : process( clk_i, clk_count )
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begin
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begin
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if rst_i = '1' then
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if rising_edge( clk_i ) then
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CountL <= "000000000000000000000000";
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if clk_count = 0 then
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elsif rising_edge(clk_i) then
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clk_count <= CPU_CLK_DIV-1;
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CountL <= CountL + 1;
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else
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clk_count <= clk_count - 1;
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end if;
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if clk_count = 0 then
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clk25 <= '0';
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elsif clk_count = (CPU_CLK_DIV/2) then
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clk25 <= '1';
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end if;
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end if;
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end if;
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--S(7 downto 0) <= CountL(23 downto 16);
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end process;
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end process;
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--
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--
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-- Generate CPU & Pixel Clock from Memory Clock
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--
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-- my_prescaler : process( clk_i, clk_count )
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-- begin
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-- if rising_edge( clk_i ) then
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-- if clk_count = 0 then
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-- clk_count <= CPU_CLK_DIV-1;
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-- else
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-- clk_count <= clk_count - 1;
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-- end if;
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-- if clk_count = 0 then
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-- clk25 <= '0';
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-- elsif clk_count = (CPU_CLK_DIV/2) then
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-- clk25 <= '1';
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-- end if;
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-- end if;
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-- end process;
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my_singlestep: btn_debounce
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port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
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SW2_N <= pbtn(0);
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SW3_N <= pbtn(1);
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clk25 <= pbtn(2);
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--
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-- Reset button and reset timer
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-- Reset button and reset timer
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--
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--
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my_switch_assignments : process( rst_i, SW2_N)
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my_switch_assignments : process( rst_i, RESET_N)
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begin
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begin
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rst_i <= SW2_N;
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rst_i <= RESET_N;
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cpu_reset <= rst_i;
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cpu_reset <= rst_i;
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end process;
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end process;
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--
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--
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-- RS232 signals:
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-- RS232 signals:
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Line 786... |
dcd_n <= '0';
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dcd_n <= '0';
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RS232_TXD <= txd;
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RS232_TXD <= txd;
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RS232_RTS <= rts_n;
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RS232_RTS <= rts_n;
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end process;
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end process;
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status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
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begin
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S(7) <= '0';
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S(6) <= cpu_rw;
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S(5) <= cpu_vma;
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S(4) <= '0';
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case sw is
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when "00000000" =>
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S(3 downto 0) <= cpu_addr(3 downto 0);
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when "00000001" =>
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S(3 downto 0) <= cpu_addr(7 downto 4);
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when "00000010" =>
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S(3 downto 0) <= cpu_addr(11 downto 8);
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when "00000011" =>
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S(3 downto 0) <= cpu_addr(15 downto 12);
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when "00000100" =>
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S(3 downto 0) <= cpu_data_in(3 downto 0);
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when "00000101" =>
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S(3 downto 0) <= cpu_data_in(7 downto 4);
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when others => S(3 downto 0) <= (others => '0');
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end case;
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end process;
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-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
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-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
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-- cpu_halt, cpu_hold,
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-- cpu_halt, cpu_hold,
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-- cpu_firq, cpu_irq, cpu_nmi,
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-- cpu_firq, cpu_irq, cpu_nmi,
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-- cpu_addr, cpu_data_out, cpu_data_in )
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-- cpu_addr, cpu_data_out, cpu_data_in )
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-- begin
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-- begin
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