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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.vhd] - Diff between revs 185 and 186

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Rev 185 Rev 186
Line 127... Line 127... 
   use unisim.vcomponents.all;
 
   use unisim.vcomponents.all;
 
 
 
 
 
entity system09 is
 
entity system09 is
 
  port(
 
  port(
 
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
 
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
 
    --SW2_N        : in  Std_logic;  -- Master Reset input (active low)
 
    --RESET_N        : in  Std_logic;  -- Master Reset input (active low)
 
    --SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
 
    --NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
 
 
 
 
 
    -- RS232 Port
 
    -- RS232 Port
 
 
 
    RS232_RTS    : out std_logic;
 
 
 
         RS232_CTS    : in  std_logic;
 
    RS232_RXD    : in  Std_Logic;
 
    RS232_RXD    : in  Std_Logic;
 
    RS232_TXD    : out Std_Logic;
 
    RS232_TXD    : out Std_Logic;
 
 
 
 
 
    -- Status 7 segment LED
 
    -- slide switches
 
         sw           : in std_logic_vector(7 downto 0);
 
         sw           : in std_logic_vector(7 downto 0);
 
 
 
         -- push buttons (Right=SS, Center=NMI, Left=RESET)
 
         btn          : in std_logic_vector(4 downto 0);
 
         btn          : in std_logic_vector(4 downto 0);
 
 
 
    -- Status 7 segment LED
 
    S            : out std_logic_vector(7 downto 0)
 
    S            : out std_logic_vector(7 downto 0)
 
 
 
 
 
 
 
 
 
-- CPU Debug Interface signals
 
-- CPU Debug Interface signals
 
--    cpu_reset_o     : out Std_Logic;
 
--    cpu_reset_o     : out Std_Logic;
Line 165... Line 169... 
architecture rtl of system09 is
 
architecture rtl of system09 is
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- constants
 
  -- constants
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
  constant CLOCK_MODE           : natural := 0; -- 0 means normal, 1 means single-step
 
 
 
 
 
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
 
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
 
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
 
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
 
 
 
 
 
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
 
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock (in Hz)
 
  constant CPU_CLK_FREQ         : natural := 1; --25_000_000;  -- CPU Clock (Hz)
 
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
 
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
 
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
 
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
 
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
 
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
 
 
 
 
  constant TRESET               : natural := 300;      -- min initialization interval (us)
 
  constant TRESET               : natural := 300;      -- min initialization interval (us)
Line 182... Line 187... 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Signals
 
  -- Signals
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  signal pbtn           : std_logic_vector(4 downto 0);
 
  signal pbtn           : std_logic_vector(4 downto 0);
 
  signal SW3_N : std_logic;
 
  signal NMI_N          : std_logic;
 
  signal SW2_N : std_logic;
 
  signal RESET_N        : std_logic;
 
 
 
  signal SINGLE_STEP    : std_logic;
 
 
 
 
 
  -- BOOT ROM
 
  -- BOOT ROM
 
  signal rom_cs         : Std_logic;
 
  signal rom_cs         : Std_logic;
 
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
 
 
 
 
  -- Flex Memory & Monitor Stack
 
  -- Flex Memory & Monitor Stack
Line 241... Line 248... 
  signal trap_irq       : std_logic;
 
  signal trap_irq       : std_logic;
 
 
 
 
 
  signal rst_i         : std_logic;     -- internal reset signal
 
  signal rst_i         : std_logic;     -- internal reset signal
 
  signal clk_i         : std_logic;     -- internal master clock signal
 
  signal clk_i         : std_logic;     -- internal master clock signal
 
 
 
 
 
  signal rs232_cts    :  Std_Logic;
 
 
 
  signal rs232_rts    :  Std_Logic;
 
 
 
 
 
 
 
  signal CountL        : std_logic_vector(23 downto 0);
 
  signal CountL        : std_logic_vector(23 downto 0);
 
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
 
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
 
  signal Clk25         : std_logic;
 
  signal Clk25         : std_logic;
 
 
 
 
 
 
 
 
Line 457... Line 461... 
    data_in  : in  std_logic_vector(7 downto 0);
 
    data_in  : in  std_logic_vector(7 downto 0);
 
    data_out : out std_logic_vector(7 downto 0)
 
    data_out : out std_logic_vector(7 downto 0)
 
  );
 
  );
 
end component;
 
end component;
 
 
 
 
 
 
 
 
 
--
 
--
 
-- Clock buffer
 
-- Clock buffer
 
--
 
--
 
 
 
 
 
component BUFG
 
component BUFG
Line 471... Line 474... 
  );
 
  );
 
end component;
 
end component;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
 
 
  --
 
 
 
  -- pushbutton debounce
 
 
 
  --
 
 
 
  my_singlestep: btn_debounce
 
 
 
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
 
 
 
 
 
 
 
  RESET_N     <= pbtn(3); -- Right PB
 
 
 
  NMI_N       <= pbtn(4); -- Center PB
 
 
 
  SINGLE_STEP <= pbtn(1); -- Left PB
 
 
 
 
 
 
 
  --
 
 
 
  -- Generate CPU & Pixel Clock from Memory Clock
 
 
 
  --
 
 
 
  NORMAL: if CLOCK_MODE = 0 generate
 
 
 
    my_prescaler : process( clk_i, clk_count )
 
 
 
    begin
 
 
 
      if rising_edge( clk_i ) then
 
 
 
        if clk_count = 0 then
 
 
 
          clk_count <= CPU_CLK_DIV-1;
 
 
 
        else
 
 
 
          clk_count <= clk_count - 1;
 
 
 
        end if;
 
 
 
        if clk_count = 0 then
 
 
 
           clk25 <= '0';
 
 
 
        elsif clk_count = (CPU_CLK_DIV/2) then
 
 
 
           clk25 <= '1';
 
 
 
        end if;
 
 
 
      end if;
 
 
 
    end process;
 
 
 
  end generate;
 
 
 
  SS: if CLOCK_MODE = 1 generate
 
 
 
    clk25 <= SINGLE_STEP;
 
 
 
  end generate;
 
 
 
 
 
 
 
  --
 
 
 
  -- Reset button and reset timer
 
 
 
  --
 
 
 
  my_switch_assignments : process( rst_i, RESET_N)
 
 
 
  begin
 
 
 
    rst_i <= RESET_N;
 
 
 
    cpu_reset <= rst_i;
 
 
 
  end process;
 
 
 
 
 
  clk_i <= CLKA;
 
  clk_i <= CLKA;
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Instantiation of internal components
 
  -- Instantiation of internal components
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
 
 
 
 
  my_cpu : cpu09
 
  my_cpu : cpu09
Line 552... Line 595... 
      data_in   => cpu_data_out,
 
      data_in   => cpu_data_out,
 
      data_out  => acia_data_out,
 
      data_out  => acia_data_out,
 
      irq       => acia_irq,
 
      irq       => acia_irq,
 
      RxC       => acia_clk,
 
      RxC       => acia_clk,
 
      TxC       => acia_clk,
 
      TxC       => acia_clk,
 
      RxD       => rxd,
 
      RxD       => RS232_RXD,
 
      TxD       => txd,
 
      TxD       => RS232_TXD,
 
      DCD_n     => dcd_n,
 
      DCD_n     => dcd_n,
 
      CTS_n     => cts_n,
 
      CTS_n     => RS232_CTS,
 
      RTS_n     => rts_n
 
      RTS_n     => RS232_RTS
 
    );
 
    );
 
 
 
  dcd_n <= '0';
 
 
 
 
 
  my_ACIA_Clock : ACIA_Clock
 
  my_ACIA_Clock : ACIA_Clock
 
    generic map(
 
    generic map(
 
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
 
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
 
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
 
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
Line 758... Line 802... 
  end process;
 
  end process;
 
 
 
 
 
  --
 
  --
 
  -- Interrupts and other bus control signals
 
  -- Interrupts and other bus control signals
 
  --
 
  --
 
  interrupts : process( SW3_N,
 
  interrupts : process( NMI_N,
 
                      acia_irq,
 
                      acia_irq,
 
                      trap_irq,
 
                      trap_irq,
 
                      timer_irq
 
                      timer_irq
 
                      )
 
                      )
 
  begin
 
  begin
 
    cpu_irq    <= acia_irq;
 
    cpu_irq    <= acia_irq;
 
    cpu_nmi    <= trap_irq or not( SW3_N );
 
    cpu_nmi    <= trap_irq or not( NMI_N );
 
    cpu_firq   <= timer_irq;
 
    cpu_firq   <= timer_irq;
 
    cpu_halt   <= '0';
 
    cpu_halt   <= '0';
 
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
 
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
 
  end process;
 
  end process;
 
 
 
 
Line 784... Line 828... 
         CountL <= CountL + 1;
 
         CountL <= CountL + 1;
 
    end if;
 
    end if;
 
    --S(7 downto 0) <= CountL(23 downto 16);
 
    --S(7 downto 0) <= CountL(23 downto 16);
 
  end process;
 
  end process;
 
 
 
 
 
  --
 
 
 
  -- Generate CPU & Pixel Clock from Memory Clock
 
 
 
  --
 
 
 
--  my_prescaler : process( clk_i, clk_count )
 
 
 
--  begin
 
 
 
--    if rising_edge( clk_i ) then
 
 
 
--      if clk_count = 0 then
 
 
 
--        clk_count <= CPU_CLK_DIV-1;
 
 
 
--      else
 
 
 
--        clk_count <= clk_count - 1;
 
 
 
--      end if;
 
 
 
--      if clk_count = 0 then
 
 
 
--         clk25 <= '0';
 
 
 
--      elsif clk_count = (CPU_CLK_DIV/2) then
 
 
 
--         clk25 <= '1';
 
 
 
--      end if;
 
 
 
--    end if;
 
 
 
--  end process;
 
 
 
 
 
 
 
 
 
 
 
  my_singlestep: btn_debounce
 
 
 
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
 
 
 
  SW2_N <= pbtn(0);
 
 
 
  SW3_N <= pbtn(1);
 
 
 
  clk25 <= pbtn(2);
 
 
 
 
 
 
 
  --
 
 
 
  -- Reset button and reset timer
 
 
 
  --
 
 
 
  my_switch_assignments : process( rst_i, SW2_N)
 
 
 
  begin
 
 
 
    rst_i <= SW2_N;
 
 
 
    cpu_reset <= rst_i;
 
 
 
  end process;
 
 
 
 
 
 
 
  --
 
 
 
  -- RS232 signals:
 
 
 
  --
 
 
 
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
 
 
 
  begin
 
 
 
    rxd       <= RS232_RXD;
 
 
 
    cts_n     <= RS232_CTS;
 
 
 
    dcd_n     <= '0';
 
 
 
    RS232_TXD <= txd;
 
 
 
    RS232_RTS <= rts_n;
 
 
 
  end process;
 
 
 
 
 
 
 
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
 
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
 
  begin
 
  begin
 
    S(7) <= '0';
 
    S(7) <= '0';
 
    S(6) <= cpu_rw;
 
    S(6) <= cpu_rw;

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