| Line 235... |
Line 235... |
signal trap_irq : std_logic;
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signal trap_irq : std_logic;
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|
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signal rst_i : std_logic; -- internal reset signal
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signal rst_i : std_logic; -- internal reset signal
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signal clk_i : std_logic; -- internal master clock signal
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signal clk_i : std_logic; -- internal master clock signal
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|
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signal CountL : std_logic_vector(23 downto 0);
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signal CountL : std_logic_vector(24 downto 0);
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal Clk25 : std_logic;
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signal Clk25 : std_logic;
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|
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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--
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--
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| Line 478... |
Line 478... |
--
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--
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-- Reset button and reset timer
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-- Reset button and reset timer
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--
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--
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my_switch_assignments : process( rst_i, RESET)
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my_switch_assignments : process( rst_i, RESET)
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begin
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begin
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rst_i <= RESET;
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rst_i <= not RESET;
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cpu_reset <= rst_i;
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cpu_reset <= rst_i;
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end process;
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end process;
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|
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clk_i <= CLKA;
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clk_i <= CLKA;
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|
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| Line 576... |
Line 576... |
begin
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begin
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RXD <= RS232_RXD;
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RXD <= RS232_RXD;
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CTS_n <= RS232_CTS;
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CTS_n <= RS232_CTS;
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DCD_n <= '0';
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DCD_n <= '0';
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RS232_TXD <= TXD;
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RS232_TXD <= TXD;
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RS232_RTS <= RTS_n;
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RS232_RTS <= not RTS_n;
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end process;
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end process;
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my_ACIA_Clock : ACIA_Clock
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my_ACIA_Clock : ACIA_Clock
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generic map(
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generic map(
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SYS_CLK_FREQ => SYS_CLK_FREQ,
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SYS_CLK_FREQ => SYS_CLK_FREQ,
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| Line 798... |
Line 798... |
-- Flash 7 segment LEDS
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-- Flash 7 segment LEDS
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--
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--
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my_led_flasher: process( clk_i, rst_i, CountL )
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my_led_flasher: process( clk_i, rst_i, CountL )
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begin
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begin
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if rst_i = '1' then
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if rst_i = '1' then
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CountL <= "000000000000000000000000";
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CountL <= "0000000000000000000000000";
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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CountL <= CountL + 1;
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CountL <= CountL + 1;
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end if;
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end if;
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end process;
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end process;
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|
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status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw)
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status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw)
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begin
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begin
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S(7) <= '0';
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S(7) <= '0';
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S(6) <= CountL(23);
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S(6) <= CountL(24);
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S(5) <= cpu_rw;
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S(5) <= cpu_reset;
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S(4) <= NMI;
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S(4) <= NMI;
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case sw is
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case sw is
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when "000" =>
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when "000" =>
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S(3 downto 0) <= cpu_addr(3 downto 0);
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S(3 downto 0) <= cpu_addr(3 downto 0);
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when "001" =>
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when "001" =>
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