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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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entity system09 is
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entity system09 is
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port(
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port(
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sysclk : in Std_Logic; -- 100MHz Clock input
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sysclk : in Std_Logic; -- 125MHz Clock input
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RESET_N : in Std_logic; -- Master Reset input (active low)
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RESET_N : in Std_logic; -- Master Reset input (active low)
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NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)
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-- RS232 Port
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-- RS232 Port
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--RS232_CTS : in std_logic;
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--RS232_CTS : in std_logic;
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architecture rtl of system09 is
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architecture rtl of system09 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- constants
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-- constants
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SYS_CLK_FREQ : natural := 100_000_000; -- FPGA System Clock (in Hz)
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constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant BAUD_RATE : integer := 57600; -- Baud Rate
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
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constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
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