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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Diff between revs 187 and 193

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Rev 187 Rev 193
Line 75... Line 75... 
 
 
 
 
entity system09 is
 
entity system09 is
 
  port(
 
  port(
 
    CLKA         : in  Std_Logic;  -- 125 MHz Clock input
 
    CLKA         : in  Std_Logic;  -- 125 MHz Clock input
 
 
 
 
 
    -- RS232 Port
 
    -- RS232 Port - via Pmod RS232
 
    RS232_RTS    : out std_logic;
 
    RS232_CTS    : in  Std_Logic;
 
         RS232_CTS    : in  std_logic;
 
    RS232_RTS    : out Std_Logic;
 
    RS232_RXD    : in  Std_Logic;
 
    RS232_RXD    : in  Std_Logic;
 
    RS232_TXD    : out Std_Logic;
 
    RS232_TXD    : out Std_Logic;
 
 
 
 
 
    -- slide switches
 
    -- slide switches
 
         sw           : in std_logic_vector(3 downto 0);
 
         sw           : in std_logic_vector(3 downto 0);
Line 110... Line 110... 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Signals
 
  -- Signals
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  signal pbtn           : std_logic_vector(3 downto 0);
 
  signal pbtn           : std_logic_vector(3 downto 0);
 
  signal NMI_N          : std_logic;
 
  signal NMI            : std_logic;
 
  signal RESET_N        : std_logic;
 
  signal RESET          : std_logic;
 
  signal SINGLE_STEP    : std_logic;
 
  signal SINGLE_STEP    : std_logic;
 
 
 
 
 
  -- BOOT ROM
 
  -- BOOT ROM
 
  signal rom_cs         : Std_logic;
 
  signal rom_cs         : Std_logic;
 
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
Line 127... Line 127... 
  -- ACIA/UART Interface signals
 
  -- ACIA/UART Interface signals
 
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
 
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
 
  signal acia_cs        : Std_Logic;
 
  signal acia_cs        : Std_Logic;
 
  signal acia_irq       : Std_Logic;
 
  signal acia_irq       : Std_Logic;
 
  signal acia_clk       : Std_Logic;
 
  signal acia_clk       : Std_Logic;
 
  signal rxd            : Std_Logic;
 
  signal RXD            : Std_Logic;
 
  signal txd            : Std_Logic;
 
  signal TXD            : Std_Logic;
 
  signal DCD_n          : Std_Logic;
 
  signal DCD_n          : Std_Logic;
 
  signal RTS_n          : Std_Logic;
 
  signal RTS_n          : Std_Logic;
 
  signal CTS_n          : Std_Logic;
 
  signal CTS_n          : Std_Logic;
 
 
 
 
 
  -- RAM
 
  -- RAM
Line 403... Line 403... 
  -- pushbutton debounce
 
  -- pushbutton debounce
 
  --
 
  --
 
  my_singlestep: btn_debounce
 
  my_singlestep: btn_debounce
 
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
 
    port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
 
 
 
 
 
  RESET_N     <= pbtn(0); -- Right PB
 
  RESET      <= pbtn(0); -- Right PB
 
  NMI_N       <= pbtn(1); -- Center PB
 
  NMI        <= pbtn(1); -- Center PB
 
  SINGLE_STEP <= pbtn(2); -- Left PB
 
  SINGLE_STEP <= pbtn(2); -- Left PB
 
 
 
 
 
  --
 
  --
 
  -- Generate CPU & Pixel Clock from Memory Clock
 
  -- Generate CPU & Pixel Clock from Memory Clock
 
  --
 
  --
Line 434... Line 434... 
  end generate;
 
  end generate;
 
 
 
 
 
  --
 
  --
 
  -- Reset button and reset timer
 
  -- Reset button and reset timer
 
  --
 
  --
 
  my_switch_assignments : process( rst_i, RESET_N)
 
  my_switch_assignments : process( rst_i, RESET)
 
  begin
 
  begin
 
    rst_i <= RESET_N;
 
    rst_i <= RESET;
 
    cpu_reset <= rst_i;
 
    cpu_reset <= rst_i;
 
  end process;
 
  end process;
 
 
 
 
 
  clk_i <= CLKA;
 
  clk_i <= CLKA;
 
 
 
 
Line 518... Line 518... 
      data_in   => cpu_data_out,
 
      data_in   => cpu_data_out,
 
      data_out  => acia_data_out,
 
      data_out  => acia_data_out,
 
      irq       => acia_irq,
 
      irq       => acia_irq,
 
      RxC       => acia_clk,
 
      RxC       => acia_clk,
 
      TxC       => acia_clk,
 
      TxC       => acia_clk,
 
      RxD       => RS232_RXD,
 
      RxD       => RXD,
 
      TxD       => RS232_TXD,
 
      TxD       => TXD,
 
      DCD_n     => dcd_n,
 
      DCD_n     => DCD_n,
 
      CTS_n     => RS232_CTS,
 
      CTS_n     => CTS_n,
 
      RTS_n     => RS232_RTS
 
      RTS_n     => RTS_n
 
    );
 
    );
 
  dcd_n <= '0';
 
 
 
 
 
  --
 
 
 
  -- RS232 signals:
 
 
 
  --
 
 
 
  my_acia_assignments : process( RS232_RXD, RS232_CTS, TXD, RTS_n )
 
 
 
  begin
 
 
 
    RXD       <= RS232_RXD;
 
 
 
    CTS_n     <= RS232_CTS;
 
 
 
    DCD_n     <= '0';
 
 
 
    RS232_TXD <= TXD;
 
 
 
    RS232_RTS <= RTS_n;
 
 
 
  end process;
 
 
 
 
 
  my_ACIA_Clock : ACIA_Clock
 
  my_ACIA_Clock : ACIA_Clock
 
    generic map(
 
    generic map(
 
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
 
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
 
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
 
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
 
    )
 
    )
 
    port map(
 
    port map(
 
      clk        => Clk_i,
 
      clk        => clk_i,
 
      acia_clk   => acia_clk
 
      acia_clk   => acia_clk
 
    );
 
    );
 
 
 
 
 
  ----------------------------------------
 
  ----------------------------------------
 
  --
 
  --
Line 692... Line 703... 
        when others =>
 
        when others =>
 
           null;
 
           null;
 
      end case;
 
      end case;
 
 
 
 
 
    --
 
    --
 
    -- Flex RAM $0C000 - $0DFFF
 
    -- Block RAM (32k) $00000 - $07FFF
 
    --
 
 
 
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
 
 
 
      cpu_data_in <= flex_data_out;
 
 
 
      flex_cs     <= cpu_vma;
 
 
 
 
 
 
 
    --
 
 
 
    -- 32k RAM $00000 - $07FFF
 
 
 
    --
 
    --
 
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
 
    elsif dat_addr(7 downto 3) = "00000"   then -- $00000 - $07FFF
 
      cpu_data_in <= ram1_data_out;
 
      cpu_data_in <= ram1_data_out;
 
      ram1_cs     <= cpu_vma;
 
      ram1_cs     <= cpu_vma;
 
 
 
 
 
    --
 
    --
 
    -- 16k RAM $08000 - $0BFFF
 
    -- Block RAM (16k) $08000 - $0BFFF
 
    --
 
    --
 
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
 
    elsif dat_addr(7 downto 2) = "000010"  then -- $08000 - $0BFFF
 
      cpu_data_in <= ram2_data_out;
 
      cpu_data_in <= ram2_data_out;
 
      ram2_cs     <= cpu_vma;
 
      ram2_cs     <= cpu_vma;
 
 
 
 
 
    --
 
    --
 
 
 
    -- Flex RAM (8k) $0C000 - $0DFFF
 
 
 
    --
 
 
 
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
 
 
 
      cpu_data_in <= flex_data_out;
 
 
 
      flex_cs     <= cpu_vma;
 
 
 
 
 
 
 
    --
 
    -- Everything else is RAM
 
    -- Everything else is RAM
 
    --
 
    --
 
    else
 
    else
 
      cpu_data_in <= (others => '0');
 
      cpu_data_in <= (others => '0');
 
      ram3_cs      <= cpu_vma;
 
      ram3_cs      <= cpu_vma;
Line 725... Line 736... 
  end process;
 
  end process;
 
 
 
 
 
  --
 
  --
 
  -- Interrupts and other bus control signals
 
  -- Interrupts and other bus control signals
 
  --
 
  --
 
  interrupts : process( NMI_N,
 
  interrupts : process( NMI,
 
                      acia_irq,
 
                      acia_irq,
 
                      trap_irq,
 
                      trap_irq,
 
                      timer_irq
 
                      timer_irq
 
                      )
 
                      )
 
  begin
 
  begin
 
    cpu_irq    <= acia_irq;
 
    cpu_irq    <= acia_irq;
 
    cpu_nmi    <= trap_irq or not( NMI_N );
 
    cpu_nmi    <= trap_irq or NMI;
 
    cpu_firq   <= timer_irq;
 
    cpu_firq   <= timer_irq;
 
    cpu_halt   <= '0';
 
    cpu_halt   <= '0';
 
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
 
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
 
  end process;
 
  end process;
 
 
 
 
Line 751... Line 762... 
         CountL <= CountL + 1;
 
         CountL <= CountL + 1;
 
    end if;
 
    end if;
 
    --S(7 downto 0) <= CountL(23 downto 16);
 
    --S(7 downto 0) <= CountL(23 downto 16);
 
  end process;
 
  end process;
 
 
 
 
 
 
 
  status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
 
 
 
 
 
 
 
 
 
  status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
 
 
 
  begin
 
  begin
 
    case sw is
 
    case sw is
 
         when "0000" =>
 
         when "0000" =>
 
           led(3 downto 0) <= cpu_addr(3 downto 0);
 
           led(3 downto 0) <= cpu_addr(3 downto 0);
 
    when "0001" =>
 
    when "0001" =>

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