| Line 86... |
Line 86... |
-- TMDS_Clk_p : out std_logic;
|
-- TMDS_Clk_p : out std_logic;
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-- TMDS_Clk_n : out std_logic;
|
-- TMDS_Clk_n : out std_logic;
|
-- TMDS_Data_p : out std_logic_vector(2 downto 0);
|
-- TMDS_Data_p : out std_logic_vector(2 downto 0);
|
-- TMDS_Data_n : out std_logic_vector(2 downto 0);
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-- TMDS_Data_n : out std_logic_vector(2 downto 0);
|
|
|
-- raw output from VDU8
|
-- CRTC output signals
|
red, green, blue, hsync, vsync, blank : out std_logic;
|
VGA_vsync_n : out Std_Logic;
|
|
VGA_hsync_n : out Std_Logic;
|
|
VGA_blue : out std_logic_vector(3 downto 0);
|
|
VGA_green : out std_logic_vector(3 downto 0);
|
|
VGA_red : out std_logic_vector(3 downto 0);
|
|
|
-- slide switches
|
-- slide switches
|
sw : in std_logic_vector(3 downto 0);
|
sw : in std_logic_vector(3 downto 0);
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-- push buttons [Unused, Single-Step, NMI, RESET]
|
-- push buttons [Unused, Single-Step, NMI, RESET]
|
btn : in std_logic_vector(3 downto 0);
|
btn : in std_logic_vector(3 downto 0);
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| Line 112... |
Line 116... |
|
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
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constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
|
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
|
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/VGA_CLK_FREQ);
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
| Line 168... |
Line 172... |
|
|
-- Dynamic Address Translation
|
-- Dynamic Address Translation
|
signal dat_cs : std_logic;
|
signal dat_cs : std_logic;
|
signal dat_addr : std_logic_vector(7 downto 0);
|
signal dat_addr : std_logic_vector(7 downto 0);
|
|
|
-- Video Display Unit (single-bit for each RGB color)
|
-- Video Display Unit
|
signal vdu_cs : std_logic;
|
signal vdu_cs : std_logic;
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
signal vga_red_o : std_logic;
|
signal vga_red_o : std_logic;
|
signal vga_green_o : std_logic;
|
signal vga_green_o : std_logic;
|
signal vga_blue_o : std_logic;
|
signal vga_blue_o : std_logic;
|
signal vga_blank_o : std_logic; -- new signal
|
|
-- original VGA interface
|
|
signal vga_vsync_n : Std_Logic;
|
|
signal vga_hsync_n : Std_Logic;
|
|
signal VGA_blue : std_logic_vector(7 downto 0);
|
|
signal VGA_green : std_logic_vector(7 downto 0);
|
|
signal VGA_red : std_logic_vector(7 downto 0);
|
|
signal vid_pData : std_logic_vector(23 downto 0);
|
|
signal serial_clk_unused : std_logic;
|
signal serial_clk_unused : std_logic;
|
-- timer
|
-- timer
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_cs : std_logic;
|
signal timer_cs : std_logic;
|
signal timer_irq : std_logic;
|
signal timer_irq : std_logic;
|
| Line 388... |
Line 385... |
-- vga port connections
|
-- vga port connections
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
vga_red_o : out std_logic;
|
vga_red_o : out std_logic;
|
vga_green_o : out std_logic;
|
vga_green_o : out std_logic;
|
vga_blue_o : out std_logic;
|
vga_blue_o : out std_logic;
|
vga_blank_o : out std_logic; -- new signal "blank"
|
|
vga_hsync_o : out std_logic;
|
vga_hsync_o : out std_logic;
|
vga_vsync_o : out std_logic
|
vga_vsync_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
| Line 643... |
Line 639... |
vdu_addr => cpu_addr(2 downto 0),
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_data_in => cpu_data_out,
|
vdu_data_in => cpu_data_out,
|
vdu_data_out => vdu_data_out,
|
vdu_data_out => vdu_data_out,
|
-- vga port connections
|
-- vga port connections
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_red_o => red,
|
vga_red_o => vga_red_o,
|
vga_green_o => green,
|
vga_green_o => vga_green_o,
|
vga_blue_o => blue,
|
vga_blue_o => vga_blue_o,
|
vga_blank_o => blank, -- new signal
|
vga_hsync_o => VGA_hsync_n,
|
vga_hsync_o => hsync,
|
vga_vsync_o => VGA_vsync_n
|
vga_vsync_o => vsync
|
|
);
|
);
|
|
--
|
|
-- VGA ouputs
|
|
--
|
|
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
|
|
begin
|
|
VGA_red(0) <= vga_red_o;
|
|
VGA_red(1) <= vga_red_o;
|
|
VGA_red(2) <= vga_red_o;
|
|
VGA_red(3) <= vga_red_o;
|
|
VGA_green(0) <= vga_green_o;
|
|
VGA_green(1) <= vga_green_o;
|
|
VGA_green(2) <= vga_green_o;
|
|
VGA_green(3) <= vga_green_o;
|
|
VGA_blue(0) <= vga_blue_o;
|
|
VGA_blue(1) <= vga_blue_o;
|
|
VGA_blue(2) <= vga_blue_o;
|
|
VGA_blue(3) <= vga_blue_o;
|
|
end process;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer Module
|
-- Timer Module
|
--
|
--
|
| Line 703... |
Line 717... |
cpu_clk_buffer : BUFG
|
cpu_clk_buffer : BUFG
|
port map(
|
port map(
|
i => Clk25,
|
i => Clk25,
|
o => cpu_clk
|
o => cpu_clk
|
);
|
);
|
|
vga_clk_buffer : BUFG
|
|
port map(
|
|
i => Clk25,
|
|
o => vga_clk
|
|
);
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
