| Line 24... |
Line 24... |
-- ieee.numeric_std
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-- ieee.numeric_std
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-- unisim.vcomponents
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-- unisim.vcomponents
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--
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--
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-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
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-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
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-- cpu09 (cpu09.vhd) CPU core
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-- cpu09 (cpu09.vhd) CPU core
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-- ACIA_6850 (ACIA_6850.vhd) ACIA / UART
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-- ACIA_6850 (acia6850.vhd) ACIA / UART
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-- (ACIA_RX.vhd)
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-- (ACIA_TX.vhd)
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-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
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-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
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-- keyboard (keyboard.vhd) PS/2 Keyboard interface
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-- keyboard (keyboard.vhd) PS/2 Keyboard interface
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-- (ps2_keyboard.vhd)
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-- (ps2_keyboard.vhd)
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-- (keymap_rom_slice.vhd) Key map table
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-- (keymap_rom_slice.vhd) Key map table
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-- vdu8_mono (vdu8_mono.vhd) Monochrome VDU
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-- vdu8_mono (vdu8_mono.vhd) Monochrome VDU
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| Line 365... |
Line 363... |
|
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component cpu09
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component cpu09
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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vma: out std_logic;
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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addr: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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rw: out std_logic; -- Asynchronous memory interface
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data_out: out std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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data_in: in std_logic_vector(7 downto 0);
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hold: in std_logic;
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irq: in std_logic;
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irq: in std_logic;
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firq: in std_logic;
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nmi: in std_logic;
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nmi: in std_logic;
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firq: in std_logic
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halt: in std_logic;
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hold: in std_logic
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);
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);
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end component;
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end component;
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|
|
|
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----------------------------------------
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----------------------------------------
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| Line 421... |
Line 419... |
--
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--
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-- 6850 Compatible ACIA / UART
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-- 6850 Compatible ACIA / UART
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--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
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|
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component ACIA_6850
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component acia6850
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port (
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port (
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clk : in Std_Logic; -- System Clock
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clk : in Std_Logic; -- System Clock
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rst : in Std_Logic; -- Reset input (active high)
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rst : in Std_Logic; -- Reset input (active high)
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cs : in Std_Logic; -- miniUART Chip Select
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cs : in Std_Logic; -- miniUART Chip Select
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rw : in Std_Logic; -- Read / Not Write
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rw : in Std_Logic; -- Read / Not Write
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addr : in Std_Logic; -- Register Select
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data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
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data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
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irq : out Std_Logic; -- Interrupt
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irq : out Std_Logic; -- Interrupt
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Addr : in Std_Logic; -- Register Select
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DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
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DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
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RxC : in Std_Logic; -- Receive Baud Clock
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RxC : in Std_Logic; -- Receive Baud Clock
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TxC : in Std_Logic; -- Transmit Baud Clock
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TxC : in Std_Logic; -- Transmit Baud Clock
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RxD : in Std_Logic; -- Receive Data
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RxD : in Std_Logic; -- Receive Data
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TxD : out Std_Logic; -- Transmit Data
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TxD : out Std_Logic; -- Transmit Data
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DCD_n : in Std_Logic; -- Data Carrier Detect
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DCD_n : in Std_Logic; -- Data Carrier Detect
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| Line 449... |
Line 447... |
--
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--
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-----------------------------------------------------------------
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-----------------------------------------------------------------
|
|
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component ACIA_Clock
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component ACIA_Clock
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generic (
|
generic (
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SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
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SYS_CLK_FREQ : integer := SYS_Clock_Frequency;
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ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
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ACIA_CLK_FREQ : integer := ACIA_Clock_Frequency
|
);
|
);
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port (
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port (
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clk : in Std_Logic; -- System Clock Input
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clk : in Std_Logic; -- System Clock Input
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ACIA_clk : out Std_logic -- ACIA Clock output
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acia_clk : out Std_logic -- ACIA Clock output
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);
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);
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end component;
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end component;
|
|
|
|
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----------------------------------------
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----------------------------------------
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| Line 467... |
Line 465... |
--
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--
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----------------------------------------
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----------------------------------------
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|
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component keyboard
|
component keyboard
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generic(
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generic(
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KBD_Clock_Frequency : integer := CPU_Clock_Frequency
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KBD_CLK_FREQ : integer := CPU_Clock_Frequency
|
);
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);
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port(
|
port(
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clk : in std_logic;
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clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
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cs : in std_logic;
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| Line 649... |
Line 647... |
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
|
|
my_cpu : cpu09 port map (
|
my_cpu : cpu09 port map (
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clk => cpu_clk,
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clk => cpu_clk,
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rst => cpu_reset,
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rst => cpu_reset,
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rw => cpu_rw,
|
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vma => cpu_vma,
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vma => cpu_vma,
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address => cpu_addr(15 downto 0),
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addr => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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rw => cpu_rw,
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data_out => cpu_data_out,
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data_out => cpu_data_out,
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halt => cpu_halt,
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data_in => cpu_data_in,
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hold => cpu_hold,
|
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irq => cpu_irq,
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irq => cpu_irq,
|
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firq => cpu_firq,
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nmi => cpu_nmi,
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nmi => cpu_nmi,
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firq => cpu_firq
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halt => cpu_halt,
|
|
hold => cpu_hold
|
);
|
);
|
|
|
my_rom : mon_rom port map (
|
my_rom : mon_rom port map (
|
clk => cpu_clk,
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clk => cpu_clk,
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rst => cpu_reset,
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rst => cpu_reset,
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| Line 681... |
Line 679... |
addr => cpu_addr(12 downto 0),
|
addr => cpu_addr(12 downto 0),
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data_out => flex_data_out,
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data_out => flex_data_out,
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data_in => cpu_data_out
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data_in => cpu_data_out
|
);
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);
|
|
|
my_acia : ACIA_6850 port map (
|
my_acia : acia6850 port map (
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clk => cpu_clk,
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clk => cpu_clk,
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rst => cpu_reset,
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rst => cpu_reset,
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cs => acia_cs,
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cs => acia_cs,
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rw => cpu_rw,
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rw => cpu_rw,
|
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addr => cpu_addr(0),
|
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data_in => cpu_data_out,
|
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data_out => acia_data_out,
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irq => acia_irq,
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irq => acia_irq,
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Addr => cpu_addr(0),
|
|
Datain => cpu_data_out,
|
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DataOut => acia_data_out,
|
|
RxC => acia_clk,
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RxC => acia_clk,
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TxC => acia_clk,
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TxC => acia_clk,
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RxD => rxd,
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RxD => rxd,
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TxD => txd,
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TxD => txd,
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DCD_n => dcd_n,
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DCD_n => dcd_n,
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| Line 702... |
Line 701... |
);
|
);
|
|
|
|
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_Clock_Frequency => SYS_Clock_Frequency,
|
SYS_CLK_FREQ => SYS_Clock_Frequency,
|
ACIA_Clock_Frequency => ACIA_Clock_Frequency
|
ACIA_CLK_FREQ => ACIA_Clock_Frequency
|
)
|
)
|
port map(
|
port map(
|
clk => Clk_i,
|
clk => Clk_i,
|
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
| Line 717... |
Line 716... |
-- PS/2 Keyboard Interface
|
-- PS/2 Keyboard Interface
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_keyboard : keyboard
|
my_keyboard : keyboard
|
generic map (
|
generic map (
|
KBD_Clock_Frequency => CPU_Clock_frequency
|
KBD_CLK_FREQ => CPU_Clock_frequency
|
)
|
)
|
port map(
|
port map(
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => keyboard_cs,
|
cs => keyboard_cs,
|
