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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XSA-3S1000/] [System09_Xess_XSA-3S1000.vhd] - Diff between revs 66 and 95

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Rev 66 Rev 95
Line 391... Line 391...
       clk   : in  std_logic;
       clk   : in  std_logic;
                 rst   : in  std_logic;
                 rst   : in  std_logic;
                 cs    : in  std_logic;
                 cs    : in  std_logic;
                 rw    : in  std_logic;
                 rw    : in  std_logic;
       addr  : in  std_logic_vector (11 downto 0);
       addr  : in  std_logic_vector (11 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
       data_in : in  std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
Line 410... Line 410...
    clk      : in  std_logic;
    clk      : in  std_logic;
    rst      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (12 downto 0);
    addr     : in  std_logic_vector (12 downto 0);
    rdata    : out std_logic_vector (7 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    wdata    : in  std_logic_vector (7 downto 0)
    data_in    : in  std_logic_vector (7 downto 0)
    );
    );
end component;
end component;
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
Line 667... Line 667...
       clk   => cpu_clk,
       clk   => cpu_clk,
                 rst   => cpu_reset,
                 rst   => cpu_reset,
                 cs    => rom_cs,
                 cs    => rom_cs,
                 rw    => '1',
                 rw    => '1',
       addr  => cpu_addr(11 downto 0),
       addr  => cpu_addr(11 downto 0),
       wdata => cpu_data_out,
       data_in => cpu_data_out,
       rdata => rom_data_out
       data_out => rom_data_out
    );
    );
 
 
my_flex : flex_ram port map (
my_flex : flex_ram port map (
    clk       => cpu_clk,
    clk       => cpu_clk,
    rst       => cpu_reset,
    rst       => cpu_reset,
         cs        => flex_cs,
         cs        => flex_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
    addr      => cpu_addr(12 downto 0),
    addr      => cpu_addr(12 downto 0),
    rdata     => flex_data_out,
    data_out     => flex_data_out,
    wdata     => cpu_data_out
    data_in     => cpu_data_out
    );
    );
 
 
my_acia  : ACIA_6850 port map (
my_acia  : ACIA_6850 port map (
         clk         => cpu_clk,
         clk         => cpu_clk,
         rst       => cpu_reset,
         rst       => cpu_reset,

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