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--
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--
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-- Description:
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-- Description:
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-- Customizes the generic SDRAM controller module for the XSA Board.
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-- Customizes the generic SDRAM controller module for the XSA Board.
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--
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--
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-- Revision:
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-- Revision:
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-- 1.1.0
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-- 1.2.0
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--
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--
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-- Additional Comments:
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-- Additional Comments:
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-- 1.2.0:
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-- added upper and lower data strobe signals
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-- John Kent 2008-03-23
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-- 1.1.0:
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-- 1.1.0:
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-- Added CLK_DIV generic parameter to allow stepping-down the clock frequency.
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-- Added CLK_DIV generic parameter to allow stepping-down the clock frequency.
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-- Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank.
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-- Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank.
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-- 1.0.0:
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-- 1.0.0:
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-- Initial release.
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-- Initial release.
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clk2x : out std_logic; -- double-speed host clock
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clk2x : out std_logic; -- double-speed host clock
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lock : out std_logic; -- true when host clock is locked to master clock
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lock : out std_logic; -- true when host clock is locked to master clock
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rst : in std_logic; -- reset
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rst : in std_logic; -- reset
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rd : in std_logic; -- initiate read operation
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rd : in std_logic; -- initiate read operation
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wr : in std_logic; -- initiate write operation
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wr : in std_logic; -- initiate write operation
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uds : in std_logic; -- upper data strobe
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lds : in std_logic; -- lower data strobe
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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done : out std_logic; -- read or write operation is done
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done : out std_logic; -- read or write operation is done
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rdDone : out std_logic; -- read done and data is available
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rdDone : out std_logic; -- read done and data is available
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clk2x : out std_logic; -- double-speed host clock
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clk2x : out std_logic; -- double-speed host clock
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lock : out std_logic; -- true when host clock is locked to master clock
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lock : out std_logic; -- true when host clock is locked to master clock
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rst : in std_logic; -- reset
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rst : in std_logic; -- reset
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rd : in std_logic; -- initiate read operation
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rd : in std_logic; -- initiate read operation
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wr : in std_logic; -- initiate write operation
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wr : in std_logic; -- initiate write operation
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uds : in std_logic; -- upper data strobe
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lds : in std_logic; -- lower data strobe
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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opBegun : out std_logic; -- read/write/self-refresh op begun (clocked)
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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rdPending : out std_logic; -- read operation(s) are still in the pipeline
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done : out std_logic; -- read or write operation is done
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done : out std_logic; -- read or write operation is done
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rdDone : out std_logic; -- read done and data is available
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rdDone : out std_logic; -- read done and data is available
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-- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges
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-- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges
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-- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM.
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-- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM.
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constant MIN_LOCK_FREQ : real := 25_000.0;
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constant MIN_LOCK_FREQ : real := 25_000.0;
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constant IN_PHASE : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ;
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constant IN_PHASE : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ;
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-- Calculate the frequency of the clock for the SDRAM.
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-- Calculate the frequency of the clock for the SDRAM.
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constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ);
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-- constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ);
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constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*2)/integer(2.0*CLK_DIV), FREQ);
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-- Compute the CLKDV_DIVIDE generic paramter for the DLL modules. It defaults to 2 when CLK_DIV=1
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-- Compute the CLKDV_DIVIDE generic paramter for the DLL modules. It defaults to 2 when CLK_DIV=1
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-- because the DLL does not support a divisor of 1 on the CLKDV output. We use the CLK0 output
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-- because the DLL does not support a divisor of 1 on the CLKDV output. We use the CLK0 output
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-- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL.
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-- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL.
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constant CLKDV_DIVIDE : real := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV);
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constant CLKDV_DIVIDE : real := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV);
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-----------------------------------------------------------
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-----------------------------------------------------------
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-- setup the DLLs for clock generation
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-- setup the DLLs for clock generation
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-----------------------------------------------------------
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-----------------------------------------------------------
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-- master clock must come from a dedicated clock pin
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-- master clock must come from a dedicated clock pin
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clkin : IBUFG port map (I => clk, O => int_clkin);
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clkin_buf : BUFG port map (I => clk, O => int_clkin);
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-- The external DLL is driven from the same source as the internal DLL
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-- The external DLL is driven from the same source as the internal DLL
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-- if the clock divisor is 1. If CLK_DIV is greater than 1, then the external DLL
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-- if the clock divisor is 1. If CLK_DIV is greater than 1, then the external DLL
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-- is driven by the divided clock from the internal DLL. Otherwise, the SDRAM will be
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-- is driven by the divided clock from the internal DLL. Otherwise, the SDRAM will be
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-- clocked on the opposite edge if the internal and external logic are not in-phase.
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-- clocked on the opposite edge if the internal and external logic are not in-phase.
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A2 => '1',
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A2 => '1',
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A3 => '1',
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A3 => '1',
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D => int_lock,
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D => int_lock,
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Q => dllext_rst_n
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Q => dllext_rst_n
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);
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);
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dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO;
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-- Error ???
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-- dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO;
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dllext_rst <= not dllext_rst_n when CLK_DIV/=1.0 else ZERO;
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-- generate an external SDRAM clock sync'ed to the master clock
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-- generate an external SDRAM clock sync'ed to the master clock
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sclkfb_buf : IBUFG port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays
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sclkfb_buf : IBUFG port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays
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-- sclkfb_buf : BUFGMUX port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays
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dllext : CLKDLL port map(
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dllext : CLKDLL port map(
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CLKIN => ext_clkin, -- this is either the master clock or the divided clock from the internal DLL
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CLKIN => ext_clkin, -- this is either the master clock or the divided clock from the internal DLL
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CLKFB => sclkfb_b,
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CLKFB => sclkfb_b,
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CLK0 => ext_clk1x,
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CLK0 => ext_clk1x,
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RST => dllext_rst,
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RST => dllext_rst,
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Line 264... |
);
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);
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end generate;
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end generate;
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-- The buffered clock is just a buffered version of the master clock.
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-- The buffered clock is just a buffered version of the master clock.
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bufclk <= int_clkin;
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bufclk_bufg : BUFG port map (I => int_clkin, O => bufclk);
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-- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1.
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-- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1.
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-- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1.
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-- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1.
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-- Otherwise it is just a copy of the master clock if the DLLs aren't being used.
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-- Otherwise it is just a copy of the master clock if the DLLs aren't being used.
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clk_i <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else
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clk_i <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else
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int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else
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int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else
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clk => clk_i, -- master clock from external clock source (unbuffered)
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clk => clk_i, -- master clock from external clock source (unbuffered)
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lock => lock_i, -- valid synchronized clocks indicator
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lock => lock_i, -- valid synchronized clocks indicator
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rst => rst, -- reset
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rst => rst, -- reset
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rd => rd, -- host-side SDRAM read control from memory tester
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rd => rd, -- host-side SDRAM read control from memory tester
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wr => wr, -- host-side SDRAM write control from memory tester
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wr => wr, -- host-side SDRAM write control from memory tester
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uds => uds, -- host-side SDRAM upper data strobe
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lds => lds, -- host-side SDRAM lower data strobe
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rdPending => rdPending,
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rdPending => rdPending,
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opBegun => opBegun, -- SDRAM memory read/write done indicator
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opBegun => opBegun, -- SDRAM memory read/write done indicator
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earlyOpBegun => earlyOpBegun, -- SDRAM memory read/write done indicator
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earlyOpBegun => earlyOpBegun, -- SDRAM memory read/write done indicator
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rdDone => rdDone, -- SDRAM memory read/write done indicator
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rdDone => rdDone, -- SDRAM memory read/write done indicator
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done => done,
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done => done,
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