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--===========================================================================----
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--===========================================================================--
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--
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-- --
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-- T E S T B E N C H tesetbench1 - CPU09 Testbench.
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-- TESTBENCH testbench1 - CPU09 Testbench. --
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--
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-- --
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-- www.OpenCores.Org - September 2003
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--===========================================================================--
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-- This core adheres to the GNU public license
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--
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--
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-- File name : Testbench1.vhd
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-- File name : Testbench1.vhd
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--
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--
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-- Purpose : cpu09 Microprocessor Test Bench 1
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-- Purpose : cpu09 Microprocessor Test Bench 1
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-- Contains ROM to print out "Hello World"
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-- Contains ROM to print out "Hello World"
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-- Uses : cpu09 (cpu09.vhd) CPU core
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-- Uses : cpu09 (cpu09.vhd) CPU core
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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-- dilbert57@opencores.org
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--
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--
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--===========================================================================----
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-- Copyright (C) 2003 - 2010 John Kent
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--
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--
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-- Revision History:
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-- This program is free software: you can redistribute it and/or modify
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--===========================================================================--
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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--
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-- Version 0.1 - 12st April 2003 - John Kent
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-- You should have received a copy of the GNU General Public License
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-- First version
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- Version 1.0- 6 Sep 2003 - John Kent
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--===========================================================================--
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-- Initial release to Open Cores
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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--
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-- Version 1.1 - 25th Jan 2004 - John Kent
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-- Rev Date Author Changes
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-- removed "test_alu" and "test_cc"
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-- 0.1 2003-04-12 John Kent First version
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-- 1.0 2003-09-06 John Kent Initial release to Opencores.org
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-- 1.1 2004-01-25 John Kent removed "test_alu" and "test_cc" from CPU component
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-- 1.2 2011-10-09 John Kent updated for acia6850
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--
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--
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--===========================================================================--
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--===========================================================================--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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-- library work;
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-- library work;
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-- use work.UART_Def.all;
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-- use work.UART_Def.all;
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-- use work.typedefines.all;
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-- use work.typedefines.all;
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-- use work.memory.all;
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-- use work.memory.all;
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entity my_testbench is
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entity my_testbench1 is
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end my_testbench;
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end my_testbench1;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-- Architecture for memio Controller Unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench is
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architecture behavior of my_testbench1 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- CPU Interface signals
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-- CPU Interface signals
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signal SysClk : Std_Logic;
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signal SysClk : Std_Logic;
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component cpu09
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component cpu09
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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rw: out std_logic; -- Asynchronous memory interface
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vma: out std_logic;
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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rw: out std_logic; -- Asynchronous memory interface
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addr: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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halt: in std_logic;
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hold: in std_logic;
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hold: in std_logic;
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irq: in std_logic;
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irq: in std_logic;
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begin
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begin
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cpu : cpu09 port map (
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cpu : cpu09 port map (
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clk => SysClk,
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clk => SysClk,
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rst => cpu_reset,
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rst => cpu_reset,
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rw => cpu_rw,
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vma => cpu_vma,
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vma => cpu_vma,
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address => cpu_addr(15 downto 0),
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rw => cpu_rw,
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addr => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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data_out => cpu_data_out,
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halt => '0',
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halt => '0',
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hold => '0',
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hold => '0',
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irq => cpu_irq,
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irq => cpu_irq,
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