| Line 1... |
Line 1... |
--===========================================================================----
|
--===========================================================================--
|
--
|
-- --
|
-- T E S T B E N C H tesetbench3 - CPU09 Testbench.
|
-- TESTBENCH testbench5 - CPU09 Testbench. --
|
--
|
-- --
|
-- www.OpenCores.Org - September 2003
|
--===========================================================================--
|
-- This core adheres to the GNU public license
|
|
--
|
--
|
-- File name : Testbench5.vhd
|
-- File name : Testbench5.vhd
|
--
|
--
|
-- Purpose : cpu09 Microprocessor Test Bench 3
|
-- Purpose : cpu09 Microprocessor Test Bench 5
|
-- Contains ROM to test interrupts
|
-- Contains ROM to test interrupts
|
--
|
--
|
-- Dependencies : ieee.Std_Logic_1164
|
-- Dependencies : ieee.Std_Logic_1164
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_arith
|
-- ieee.std_logic_arith
|
-- ieee.numeric_std
|
-- ieee.numeric_std
|
--
|
--
|
-- Uses : cpu09 (cpu09.vhd) CPU core
|
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core
|
--
|
--
|
-- Author : John E. Kent
|
-- Author : John E. Kent
|
-- dilbert57@opencores.org
|
-- dilbert57@opencores.org
|
--
|
--
|
--===========================================================================----
|
-- Copyright (C) 2003 - 2011 John Kent
|
--
|
--
|
-- Revision History:
|
-- This program is free software: you can redistribute it and/or modify
|
--===========================================================================--
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- This program is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
--
|
--
|
-- Version 0.1 - 12st April 2003 - John Kent
|
-- You should have received a copy of the GNU General Public License
|
-- First version
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
--
|
--
|
-- Version 1.0 - 6 Sep 2003 - John Kent
|
--===========================================================================--
|
-- Initial release to Open Cores
|
-- --
|
|
-- Revision History --
|
|
-- --
|
|
--===========================================================================--
|
--
|
--
|
-- Version 1.1 - 25th Jan 2004 - John Kent
|
-- Rev Date Author Changes
|
-- removed "test_alu" and "test_cc"
|
-- 0.1 2003-04-12 John Kent First version
|
|
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org
|
|
-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component.
|
|
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header
|
--
|
--
|
--===========================================================================--
|
--===========================================================================--
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
| Line 124... |
Line 136... |
port (
|
port (
|
clk: in std_logic;
|
clk: in std_logic;
|
rst: in std_logic;
|
rst: in std_logic;
|
rw: out std_logic; -- Asynchronous memory interface
|
rw: out std_logic; -- Asynchronous memory interface
|
vma: out std_logic;
|
vma: out std_logic;
|
address: out std_logic_vector(15 downto 0);
|
addr: out std_logic_vector(15 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
halt: in std_logic;
|
halt: in std_logic;
|
hold: in std_logic;
|
hold: in std_logic;
|
irq: in std_logic;
|
irq: in std_logic;
|
| Line 142... |
Line 154... |
cpu : cpu09 port map (
|
cpu : cpu09 port map (
|
clk => SysClk,
|
clk => SysClk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
address => cpu_addr(15 downto 0),
|
addr => cpu_addr(15 downto 0),
|
data_in => cpu_data_in,
|
data_in => cpu_data_in,
|
data_out => cpu_data_out,
|
data_out => cpu_data_out,
|
halt => '0',
|
halt => '0',
|
hold => '0',
|
hold => '0',
|
irq => cpu_irq,
|
irq => cpu_irq,
|
