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--===========================================================================----
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--===========================================================================
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--
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--
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-- S Y N T H E Z I A B L E Clock_dll for System09 - SOC.
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-- clock_div.vhd - Clock divider for System09
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--
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--
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--===========================================================================----
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--===========================================================================
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--
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--
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-- This core adheres to the GNU public license
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-- File name : clock_div.vhd
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-- No responsibility is taken for this design.
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-- Use at own risk.
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--
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--
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-- File name : Clock_dll.vhd
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-- Entity name : clock_div
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--
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--
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-- Purpose : Generates Clocks for System09
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-- Purpose : Generates Clocks for System09
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-- For BurchED B3-Spartan2+ and B5-X300
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-- For BurchED B3-Spartan2+ and B5-X300
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-- Assumes a 12.5 MHz system clock input
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-- Divides the input clock which is normally 50MHz
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-- Generates a x1 (12.5 MHz) CPU clock
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-- Generates a 1/1 (50.0 MHz) SYS clock
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-- Generates a x2 (25.0 MHz) VGA clock
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-- Generates a 1/2 (25.0 MHz) VGA clock
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-- Generates a x4 (50.0 MHz) MEM clock
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-- Generates a 1/4 (12.5 MHz) CPU clock
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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-- ieee.numeric_std
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--
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--
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-- Uses : IBUFG
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-- BUFG
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--
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================
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--
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--
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-- Revision History :
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-- Revision History :
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--
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--
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-- Rev : 0.1
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--===========================================================================
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-- Date : 7th September 2008
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--
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-- Description : Initial version.
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-- Rev: Date: Author: Description:
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--
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-- 0.1 2008-09-07 John Kent Initial version
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-- 0.2 2010-09-14 John Kent Updated header
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library unisim;
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--library unisim;
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use unisim.vcomponents.all;
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-- use unisim.vcomponents.all;
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entity clock_div is
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entity clock_div is
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port(
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port(
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clk_in : in std_Logic; -- System Clock input
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clk_in : in std_Logic; -- System Clock input
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sys_clk : out std_logic; -- System Clock Out (1/1)
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sys_clk : out std_logic; -- System Clock Out (1/1)
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| Line 47... |
Line 70... |
);
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);
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end entity;
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end entity;
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architecture RTL of clock_div is
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architecture RTL of clock_div is
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signal div_clk : std_logic;
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signal div_count : std_logic_vector(1 downto 0);
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signal div_count : std_logic_vector(1 downto 0);
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component IBUFG
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port (
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i: in std_logic;
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o: out std_logic
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);
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end component;
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component BUFG
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component BUFG
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port (
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port (
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i: in std_logic;
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i: in std_logic;
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o: out std_logic
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o: out std_logic
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);
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);
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end component;
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end component;
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--
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--
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-- Start instantiation
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-- Start instantiation
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--
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--
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begin
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begin
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|
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--
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--
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-- 50.0MHz system clock
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-- 50 MHz SYS clock output
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--
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--
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sys_clk_buffer : IBUFG
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sys_clk_buffer : BUFG
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port map(
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port map(
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i => clk_in,
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i => clk_in,
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o => div_clk
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o => sys_clk
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);
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);
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--
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--
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-- 25 MHz VGA clock output
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-- 25 MHz VGA clock output
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--
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--
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| Line 100... |
Line 114... |
);
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);
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--
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--
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-- Clock divider
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-- Clock divider
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--
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--
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clock_div : process( div_clk )
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clock_div : process( clk_in )
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begin
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begin
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if rising_edge( div_clk) then
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if rising_edge( clk_in ) then
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div_count <= div_count + "01";
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div_count <= div_count + "01";
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end if;
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end if;
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sys_clk <= div_clk;
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end process;
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end process;
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end architecture;
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end architecture;
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