| Line 1... |
Line 1... |
-- $Id: cpu09.vhd,v 1.1 2007-12-09 16:06:03 dilbert57 Exp $
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-- $Id: cpu09.vhd,v 1.2 2008-03-14 15:52:46 dilbert57 Exp $
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--===========================================================================----
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--===========================================================================----
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--
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--
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-- S Y N T H E Z I A B L E CPU09 - 6809 compatible CPU Core
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-- S Y N T H E Z I A B L E CPU09 - 6809 compatible CPU Core
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--
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--
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-- www.OpenCores.Org - September 2003
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-- www.OpenCores.Org - September 2003
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| Line 142... |
Line 142... |
--
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--
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-- Version 1.15 - 25th Feb 2007 - John Kent
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-- Version 1.15 - 25th Feb 2007 - John Kent
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-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
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-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
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-- Changed sensitivity lists.
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-- Changed sensitivity lists.
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--
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--
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-- Version 1.16 - 5th February 2008 - John Kent
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-- FIRQ interrupts should take priority over IRQ Interrupts.
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-- This presumably means they should be tested for before IRQ
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-- when they happen concurrently.
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--
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-- Version 1.17 - 18th February 2008 - John Kent
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-- NMI in CWAI should mask IRQ and FIRQ interrupts
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--
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-- Version 1.18 - 21st February 2008 - John Kent
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-- Removed default register settings in each case statement
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-- and placed them at the beginning of the state sequencer.
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-- Modified the SYNC instruction so that the interrupt vector(iv)
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-- is not set unless an unmasked FIRQ or IRQ is received.
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--
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-- Version 1.19 - 25th February 2008 - John Kent
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-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
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-- Enumerated separate states for MASKI and MASKIF states
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-- Removed code on BSR/JSR in fetch cycle
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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entity cpu09 is
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entity cpu09 is
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| Line 226... |
Line 245... |
-- Jumps, Subroutine Calls and Returns
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-- Jumps, Subroutine Calls and Returns
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jsr_state, jmp_state,
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jsr_state, jmp_state,
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push_return_hi_state, push_return_lo_state,
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push_return_hi_state, push_return_lo_state,
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pull_return_hi_state, pull_return_lo_state,
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pull_return_hi_state, pull_return_lo_state,
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-- Interrupt cycles
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-- Interrupt cycles
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int_decr_state,
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int_nmiirq_state, int_firq_state,
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int_entire_state,
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int_entire_state, int_fast_state,
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int_pcl_state, int_pch_state,
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int_pcl_state, int_pch_state,
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int_upl_state, int_uph_state,
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int_upl_state, int_uph_state,
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int_iyl_state, int_iyh_state,
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int_iyl_state, int_iyh_state,
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int_ixl_state, int_ixh_state,
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int_ixl_state, int_ixh_state,
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int_cc_state,
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int_acca_state, int_accb_state,
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int_dp_state,
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int_dp_state,
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int_cwai_state, int_mask_state,
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int_accb_state, int_acca_state,
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int_cc_state,
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int_cwai_state,
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int_maski_state, int_maskif_state,
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-- Return From Interrupt
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-- Return From Interrupt
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rti_cc_state, rti_entire_state,
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rti_cc_state, rti_entire_state,
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rti_acca_state, rti_accb_state,
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rti_acca_state, rti_accb_state,
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rti_dp_state,
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rti_dp_state,
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rti_ixl_state, rti_ixh_state,
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rti_ixl_state, rti_ixh_state,
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| Line 301... |
Line 321... |
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
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type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
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type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
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type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
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type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
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type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
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type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
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type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
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type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
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type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
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type iv_type is (reset_iv, latch_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
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type iv_type is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
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type nmi_type is (reset_nmi, set_nmi, latch_nmi );
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type nmi_type is (reset_nmi, set_nmi, latch_nmi );
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type left_type is (cc_left, acca_left, accb_left, dp_left,
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type left_type is (cc_left, acca_left, accb_left, dp_left,
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ix_left, iy_left, up_left, sp_left,
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ix_left, iy_left, up_left, sp_left,
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accd_left, md_left, pc_left, ea_left );
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accd_left, md_left, pc_left, ea_left );
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type right_type is (ea_right, zero_right, one_right, two_right,
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type right_type is (ea_right, zero_right, one_right, two_right,
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| Line 975... |
Line 995... |
--
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--
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--------------------------------
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--------------------------------
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dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
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dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
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begin
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begin
|
case dout_ctrl is
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case dout_ctrl is
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when md_hi_dout => -- alu output
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when cc_dout => -- condition code register
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data_out <= md(15 downto 8);
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data_out <= cc;
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when md_lo_dout => -- alu output
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|
data_out <= md(7 downto 0);
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when acca_dout => -- accumulator a
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when acca_dout => -- accumulator a
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data_out <= acca;
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data_out <= acca;
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when accb_dout => -- accumulator b
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when accb_dout => -- accumulator b
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data_out <= accb;
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data_out <= accb;
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when ix_lo_dout => -- index reg
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when dp_dout => -- direct page register
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data_out <= dp;
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when ix_lo_dout => -- X index reg
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data_out <= xreg(7 downto 0);
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data_out <= xreg(7 downto 0);
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when ix_hi_dout => -- index reg
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when ix_hi_dout => -- X index reg
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data_out <= xreg(15 downto 8);
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data_out <= xreg(15 downto 8);
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when iy_lo_dout => -- index reg
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when iy_lo_dout => -- Y index reg
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data_out <= yreg(7 downto 0);
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data_out <= yreg(7 downto 0);
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when iy_hi_dout => -- index reg
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when iy_hi_dout => -- Y index reg
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data_out <= yreg(15 downto 8);
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data_out <= yreg(15 downto 8);
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when sp_lo_dout => -- s stack pointer
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when up_lo_dout => -- U stack pointer
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data_out <= sp(7 downto 0);
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when sp_hi_dout => -- s stack pointer
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data_out <= sp(15 downto 8);
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when up_lo_dout => -- u stack pointer
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data_out <= up(7 downto 0);
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data_out <= up(7 downto 0);
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when up_hi_dout => -- u stack pointer
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when up_hi_dout => -- U stack pointer
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data_out <= up(15 downto 8);
|
data_out <= up(15 downto 8);
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when cc_dout => -- condition code register
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when sp_lo_dout => -- S stack pointer
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data_out <= cc;
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data_out <= sp(7 downto 0);
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when dp_dout => -- direct page register
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when sp_hi_dout => -- S stack pointer
|
data_out <= dp;
|
data_out <= sp(15 downto 8);
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when md_lo_dout => -- alu output
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data_out <= md(7 downto 0);
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when md_hi_dout => -- alu output
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data_out <= md(15 downto 8);
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when pc_lo_dout => -- low order pc
|
when pc_lo_dout => -- low order pc
|
data_out <= pc(7 downto 0);
|
data_out <= pc(7 downto 0);
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when pc_hi_dout => -- high order pc
|
when pc_hi_dout => -- high order pc
|
data_out <= pc(15 downto 8);
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data_out <= pc(15 downto 8);
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when others =>
|
when others =>
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| Line 1438... |
Line 1458... |
op_code, pre_code,
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op_code, pre_code,
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cc, ea, md, iv,
|
cc, ea, md, iv,
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irq, firq, nmi_req, nmi_ack, halt )
|
irq, firq, nmi_req, nmi_ack, halt )
|
variable cond_true : boolean; -- variable used to evaluate coditional branches
|
variable cond_true : boolean; -- variable used to evaluate coditional branches
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begin
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begin
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-- Registers preserved
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cc_ctrl <= latch_cc;
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acca_ctrl <= latch_acca;
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accb_ctrl <= latch_accb;
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dp_ctrl <= latch_dp;
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ix_ctrl <= latch_ix;
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iy_ctrl <= latch_iy;
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up_ctrl <= latch_up;
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sp_ctrl <= latch_sp;
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pc_ctrl <= latch_pc;
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md_ctrl <= latch_md;
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ea_ctrl <= latch_ea;
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iv_ctrl <= latch_iv;
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op_ctrl <= latch_op;
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pre_ctrl <= latch_pre;
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nmi_ctrl <= latch_nmi;
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-- ALU Idle
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left_ctrl <= pc_left;
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right_ctrl <= zero_right;
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alu_ctrl <= alu_nop;
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-- Bus idle
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addr_ctrl <= idle_ad;
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dout_ctrl <= cc_dout;
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-- Next State Fetch
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st_ctrl <= idle_st;
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return_state <= fetch_state;
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next_state <= fetch_state;
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|
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case state is
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case state is
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when reset_state => -- released from reset
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when reset_state => -- released from reset
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-- reset the registers
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-- reset the registers
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op_ctrl <= reset_op;
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op_ctrl <= reset_op;
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pre_ctrl <= reset_pre;
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pre_ctrl <= reset_pre;
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cc_ctrl <= reset_cc;
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acca_ctrl <= reset_acca;
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acca_ctrl <= reset_acca;
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accb_ctrl <= reset_accb;
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accb_ctrl <= reset_accb;
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dp_ctrl <= reset_dp;
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ix_ctrl <= reset_ix;
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ix_ctrl <= reset_ix;
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iy_ctrl <= reset_iy;
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iy_ctrl <= reset_iy;
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sp_ctrl <= reset_sp;
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up_ctrl <= reset_up;
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up_ctrl <= reset_up;
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sp_ctrl <= reset_sp;
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pc_ctrl <= reset_pc;
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pc_ctrl <= reset_pc;
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ea_ctrl <= reset_ea;
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ea_ctrl <= reset_ea;
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md_ctrl <= reset_md;
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md_ctrl <= reset_md;
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iv_ctrl <= reset_iv;
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iv_ctrl <= reset_iv;
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nmi_ctrl <= reset_nmi;
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nmi_ctrl <= reset_nmi;
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-- idle the ALU
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left_ctrl <= pc_left;
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right_ctrl <= zero_right;
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alu_ctrl <= alu_nop;
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cc_ctrl <= reset_cc;
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dp_ctrl <= reset_dp;
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-- idle the bus
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dout_ctrl <= md_lo_dout;
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addr_ctrl <= idle_ad;
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st_ctrl <= idle_st;
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return_state <= vect_hi_state;
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next_state <= vect_hi_state;
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next_state <= vect_hi_state;
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|
|
--
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--
|
-- Jump via interrupt vector
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-- Jump via interrupt vector
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-- iv holds interrupt type
|
-- iv holds interrupt type
|
-- fetch PC hi from vector location
|
-- fetch PC hi from vector location
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--
|
--
|
when vect_hi_state =>
|
when vect_hi_state =>
|
-- default the registers
|
|
op_ctrl <= latch_op;
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pre_ctrl <= latch_pre;
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nmi_ctrl <= latch_nmi;
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acca_ctrl <= latch_acca;
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accb_ctrl <= latch_accb;
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ix_ctrl <= latch_ix;
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iy_ctrl <= latch_iy;
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sp_ctrl <= latch_sp;
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up_ctrl <= latch_up;
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md_ctrl <= latch_md;
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ea_ctrl <= latch_ea;
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|
iv_ctrl <= latch_iv;
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|
-- idle the ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
-- fetch pc low interrupt vector
|
-- fetch pc low interrupt vector
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= int_hi_ad;
|
addr_ctrl <= int_hi_ad;
|
dout_ctrl <= pc_hi_dout;
|
|
st_ctrl <= idle_st;
|
|
return_state <= vect_lo_state;
|
|
next_state <= vect_lo_state;
|
next_state <= vect_lo_state;
|
--
|
--
|
-- jump via interrupt vector
|
-- jump via interrupt vector
|
-- iv holds vector type
|
-- iv holds vector type
|
-- fetch PC lo from vector location
|
-- fetch PC lo from vector location
|
--
|
--
|
when vect_lo_state =>
|
when vect_lo_state =>
|
-- default the registers
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
ea_ctrl <= latch_ea;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
-- fetch the vector low byte
|
-- fetch the vector low byte
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= int_lo_ad;
|
addr_ctrl <= int_lo_ad;
|
dout_ctrl <= pc_lo_dout;
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
--
|
--
|
-- Here to fetch an instruction
|
-- Here to fetch an instruction
|
-- PC points to opcode
|
-- PC points to opcode
|
-- Should service interrupt requests at this point
|
-- Should service interrupt requests at this point
|
| Line 1543... |
Line 1538... |
when fetch_state =>
|
when fetch_state =>
|
-- fetch the op code
|
-- fetch the op code
|
op_ctrl <= fetch_op;
|
op_ctrl <= fetch_op;
|
pre_ctrl <= fetch_pre;
|
pre_ctrl <= fetch_pre;
|
ea_ctrl <= reset_ea;
|
ea_ctrl <= reset_ea;
|
md_ctrl <= latch_md;
|
|
-- Fetch op code
|
-- Fetch op code
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
dp_ctrl <= latch_dp;
|
|
--
|
--
|
case op_code(7 downto 6) is
|
case op_code(7 downto 6) is
|
when "10" => -- acca
|
when "10" => -- acca
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- suba
|
when "0000" => -- suba
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0001" => -- cmpa
|
when "0001" => -- cmpa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0010" => -- sbca
|
when "0010" => -- sbca
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sbc;
|
alu_ctrl <= alu_sbc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0011" =>
|
when "0011" =>
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- cmpd
|
when "00010000" => -- page 2 -- cmpd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "00010001" => -- page 3 -- cmpu
|
when "00010001" => -- page 3 -- cmpu
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when others => -- page 1 -- subd
|
when others => -- page 1 -- subd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when "0100" => -- anda
|
when "0100" => -- anda
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0101" => -- bita
|
when "0101" => -- bita
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0110" => -- ldaa
|
when "0110" => -- ldaa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld8;
|
alu_ctrl <= alu_ld8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0111" => -- staa
|
when "0111" => -- staa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1000" => -- eora
|
when "1000" => -- eora
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_eor;
|
alu_ctrl <= alu_eor;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1001" => -- adca
|
when "1001" => -- adca
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_adc;
|
alu_ctrl <= alu_adc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1010" => -- oraa
|
when "1010" => -- oraa
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ora;
|
alu_ctrl <= alu_ora;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1011" => -- adda
|
when "1011" => -- adda
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add8;
|
alu_ctrl <= alu_add8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1100" =>
|
when "1100" =>
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- cmpy
|
when "00010000" => -- page 2 -- cmpy
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "00010001" => -- page 3 -- cmps
|
when "00010001" => -- page 3 -- cmps
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when others => -- page 1 -- cmpx
|
when others => -- page 1 -- cmpx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when "1101" => -- bsr / jsr
|
when "1101" => -- bsr / jsr
|
left_ctrl <= pc_left;
|
null;
|
right_ctrl <= md_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1110" => -- ldx
|
when "1110" => -- ldx
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- ldy
|
when "00010000" => -- page 2 -- ldy
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when others => -- page 1 -- ldx
|
when others => -- page 1 -- ldx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when "1111" => -- stx
|
when "1111" => -- stx
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sty
|
when "00010000" => -- page 2 -- sty
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when others => -- page 1 -- stx
|
when others => -- page 1 -- stx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when others =>
|
when others =>
|
null;
|
null;
|
-- left_ctrl <= acca_left;
|
|
-- right_ctrl <= md_right;
|
|
-- alu_ctrl <= alu_nop;
|
|
-- cc_ctrl <= latch_cc;
|
|
-- acca_ctrl <= latch_acca;
|
|
-- accb_ctrl <= latch_accb;
|
|
-- ix_ctrl <= latch_ix;
|
|
-- iy_ctrl <= latch_iy;
|
|
-- up_ctrl <= latch_up;
|
|
-- sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when "11" => -- accb dual op
|
when "11" => -- accb dual op
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- subb
|
when "0000" => -- subb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0001" => -- cmpb
|
when "0001" => -- cmpb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sub8;
|
alu_ctrl <= alu_sub8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0010" => -- sbcb
|
when "0010" => -- sbcb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_sbc;
|
alu_ctrl <= alu_sbc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0011" => -- addd
|
when "0011" => -- addd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0100" => -- andb
|
when "0100" => -- andb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0101" => -- bitb
|
when "0101" => -- bitb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_and;
|
alu_ctrl <= alu_and;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0110" => -- ldab
|
when "0110" => -- ldab
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld8;
|
alu_ctrl <= alu_ld8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0111" => -- stab
|
when "0111" => -- stab
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1000" => -- eorb
|
when "1000" => -- eorb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_eor;
|
alu_ctrl <= alu_eor;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1001" => -- adcb
|
when "1001" => -- adcb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_adc;
|
alu_ctrl <= alu_adc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1010" => -- orab
|
when "1010" => -- orab
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ora;
|
alu_ctrl <= alu_ora;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1011" => -- addb
|
when "1011" => -- addb
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add8;
|
alu_ctrl <= alu_add8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1100" => -- ldd
|
when "1100" => -- ldd
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1101" => -- std
|
when "1101" => -- std
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "1110" => -- ldu
|
when "1110" => -- ldu
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- lds
|
when "00010000" => -- page 2 -- lds
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
when others => -- page 1 -- ldu
|
when others => -- page 1 -- ldu
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when "1111" =>
|
when "1111" =>
|
case pre_code is
|
case pre_code is
|
when "00010000" => -- page 2 -- sts
|
when "00010000" => -- page 2 -- sts
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when others => -- page 1 -- stu
|
when others => -- page 1 -- stu
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when others =>
|
when others =>
|
null;
|
null;
|
-- left_ctrl <= accb_left;
|
|
-- right_ctrl <= md_right;
|
|
-- alu_ctrl <= alu_nop;
|
|
-- cc_ctrl <= latch_cc;
|
|
-- acca_ctrl <= latch_acca;
|
|
-- accb_ctrl <= latch_accb;
|
|
-- ix_ctrl <= latch_ix;
|
|
-- iy_ctrl <= latch_iy;
|
|
-- up_ctrl <= latch_up;
|
|
-- sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
when others =>
|
when others =>
|
left_ctrl <= acca_left;
|
null;
|
right_ctrl <= md_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
if halt = '1' then
|
if halt = '1' then
|
iv_ctrl <= reset_iv;
|
iv_ctrl <= reset_iv;
|
pc_ctrl <= latch_pc;
|
|
nmi_ctrl <= latch_nmi;
|
|
st_ctrl <= push_st;
|
|
return_state <= fetch_state;
|
|
next_state <= halt_state;
|
next_state <= halt_state;
|
-- service non maskable interrupts
|
-- service non maskable interrupts
|
elsif (nmi_req = '1') and (nmi_ack = '0') then
|
elsif (nmi_req = '1') and (nmi_ack = '0') then
|
iv_ctrl <= nmi_iv;
|
iv_ctrl <= nmi_iv;
|
pc_ctrl <= latch_pc;
|
|
nmi_ctrl <= set_nmi;
|
nmi_ctrl <= set_nmi;
|
st_ctrl <= idle_st;
|
next_state <= int_nmiirq_state;
|
return_state <= fetch_state;
|
|
next_state <= int_decr_state;
|
|
-- service maskable interrupts
|
-- service maskable interrupts
|
else
|
else
|
--
|
--
|
-- nmi request is not cleared until nmi input goes low
|
-- nmi request is not cleared until nmi input goes low
|
--
|
--
|
if(nmi_req = '0') and (nmi_ack='1') then
|
if(nmi_req = '0') and (nmi_ack='1') then
|
nmi_ctrl <= reset_nmi;
|
nmi_ctrl <= reset_nmi;
|
else
|
|
nmi_ctrl <= latch_nmi;
|
|
end if;
|
end if;
|
--
|
--
|
-- IRQ is level sensitive
|
-- FIRQ & IRQ are level sensitive
|
--
|
--
|
if (irq = '1') and (cc(IBIT) = '0') then
|
if (firq = '1') and (cc(FBIT) = '0') then
|
iv_ctrl <= irq_iv;
|
|
pc_ctrl <= latch_pc;
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_decr_state;
|
|
elsif (firq = '1') and (cc(FBIT) = '0') then
|
|
iv_ctrl <= firq_iv;
|
iv_ctrl <= firq_iv;
|
pc_ctrl <= latch_pc;
|
next_state <= int_firq_state;
|
st_ctrl <= idle_st;
|
elsif (irq = '1') and (cc(IBIT) = '0') then
|
return_state <= fetch_state;
|
iv_ctrl <= irq_iv;
|
next_state <= int_decr_state;
|
next_state <= int_nmiirq_state;
|
else
|
else
|
-- Advance the PC to fetch next instruction byte
|
-- Advance the PC to fetch next instruction byte
|
iv_ctrl <= reset_iv; -- default to reset
|
iv_ctrl <= reset_iv; -- default to reset
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= decode1_state;
|
next_state <= decode1_state;
|
end if;
|
end if;
|
end if;
|
end if;
|
--
|
--
|
-- Here to decode instruction
|
-- Here to decode instruction
|
-- and fetch next byte of intruction
|
-- and fetch next byte of intruction
|
-- whether it be necessary or not
|
-- whether it be necessary or not
|
--
|
--
|
when decode1_state =>
|
when decode1_state =>
|
pre_ctrl <= latch_pre;
|
|
-- fetch first byte of address or immediate data
|
-- fetch first byte of address or immediate data
|
ea_ctrl <= fetch_first_ea;
|
ea_ctrl <= fetch_first_ea;
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
nmi_ctrl <= latch_nmi;
|
|
dp_ctrl <= latch_dp;
|
|
case op_code(7 downto 4) is
|
case op_code(7 downto 4) is
|
--
|
--
|
-- direct single op (2 bytes)
|
-- direct single op (2 bytes)
|
-- 6809 => 6 cycles
|
-- 6809 => 6 cycles
|
-- cpu09 => 5 cycles
|
-- cpu09 => 5 cycles
|
| Line 2132... |
Line 1857... |
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
|
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
|
-- 3 pc=ea
|
-- 3 pc=ea
|
--
|
--
|
when "0000" =>
|
when "0000" =>
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- advance the PC
|
-- advance the PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
next_state <= jmp_state;
|
next_state <= jmp_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
next_state <= single_op_exec_state;
|
next_state <= single_op_exec_state;
|
| Line 2161... |
Line 1870... |
next_state <= single_op_read_state;
|
next_state <= single_op_read_state;
|
end case;
|
end case;
|
|
|
-- acca / accb inherent instructions
|
-- acca / accb inherent instructions
|
when "0001" =>
|
when "0001" =>
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
--
|
--
|
-- Page2 pre byte
|
-- Page2 pre byte
|
-- pre=(pc) / pc=pc+1
|
-- pre=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
--
|
--
|
when "0000" => -- page2
|
when "0000" => -- page2
|
op_ctrl <= fetch_op;
|
op_ctrl <= fetch_op;
|
acca_ctrl <= latch_acca;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- advance pc
|
-- advance pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= decode2_state;
|
next_state <= decode2_state;
|
|
|
--
|
--
|
-- Page3 pre byte
|
-- Page3 pre byte
|
-- pre=(pc) / pc=pc+1
|
-- pre=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
-- op=(pc) / pc=pc+1
|
--
|
--
|
when "0001" => -- page3
|
when "0001" => -- page3
|
op_ctrl <= fetch_op;
|
op_ctrl <= fetch_op;
|
acca_ctrl <= latch_acca;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- advance pc
|
-- advance pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- Next state
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= decode3_state;
|
next_state <= decode3_state;
|
|
|
--
|
--
|
-- nop - No operation ( 1 byte )
|
-- nop - No operation ( 1 byte )
|
-- 6809 => 2 cycles
|
-- 6809 => 2 cycles
|
-- cpu09 => 2 cycles
|
-- cpu09 => 2 cycles
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 decode
|
-- 2 decode
|
--
|
--
|
when "0010" => -- nop
|
when "0010" => -- nop
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
--
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- sync - halt execution until an interrupt is received
|
-- sync - halt execution until an interrupt is received
|
-- interrupt may be NMI, IRQ or FIRQ
|
-- interrupt may be NMI, IRQ or FIRQ
|
| Line 2241... |
Line 1912... |
-- interrupt is asserted for 3 clock cycles
|
-- interrupt is asserted for 3 clock cycles
|
-- note that registers are not pushed onto the stack
|
-- note that registers are not pushed onto the stack
|
-- CPU09 => Interrupts need only be asserted for one clock cycle
|
-- CPU09 => Interrupts need only be asserted for one clock cycle
|
--
|
--
|
when "0011" => -- sync
|
when "0011" => -- sync
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
--
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= sync_state;
|
next_state <= sync_state;
|
|
|
--
|
--
|
-- lbra -- long branch (3 bytes)
|
-- lbra -- long branch (3 bytes)
|
-- 6809 => 5 cycles
|
-- 6809 => 5 cycles
|
| Line 2266... |
Line 1924... |
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 4 pc=pc+md
|
-- 4 pc=pc+md
|
--
|
--
|
when "0110" =>
|
when "0110" =>
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= lbranch_state;
|
next_state <= lbranch_state;
|
|
|
--
|
--
|
-- lbsr - long branch to subroutine (3 bytes)
|
-- lbsr - long branch to subroutine (3 bytes)
|
-- 6809 => 9 cycles
|
-- 6809 => 9 cycles
|
| Line 2293... |
Line 1940... |
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
|
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
|
-- 5 (sp)=pc_hi / pc=pc
|
-- 5 (sp)=pc_hi / pc=pc
|
-- 6 pc=pc+md
|
-- 6 pc=pc+md
|
--
|
--
|
when "0111" =>
|
when "0111" =>
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
-- pre decrement sp
|
-- pre decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= lbranch_state;
|
next_state <= lbranch_state;
|
|
|
when "1001" => -- daa
|
when "1001" => -- daa
|
op_ctrl <= latch_op;
|
|
--
|
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= accb_right;
|
right_ctrl <= accb_right;
|
alu_ctrl <= alu_daa;
|
alu_ctrl <= alu_daa;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
sp_ctrl <= latch_sp;
|
|
-- idle pc
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when "1010" => -- orcc
|
when "1010" => -- orcc
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- next state
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= orcc_state;
|
next_state <= orcc_state;
|
|
|
when "1100" => -- andcc
|
when "1100" => -- andcc
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= andcc_state;
|
next_state <= andcc_state;
|
|
|
when "1101" => -- sex
|
when "1101" => -- sex
|
op_ctrl <= latch_op;
|
|
-- have sex
|
-- have sex
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_sex;
|
alu_ctrl <= alu_sex;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
sp_ctrl <= latch_sp;
|
|
-- idle PC
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when "1110" => -- exg
|
when "1110" => -- exg
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= exg_state;
|
next_state <= exg_state;
|
|
|
when "1111" => -- tfr
|
when "1111" => -- tfr
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- call transfer as a subroutine
|
-- call transfer as a subroutine
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= tfr_state;
|
next_state <= tfr_state;
|
|
|
when others =>
|
when others =>
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
--
|
--
|
-- Short branch conditional
|
-- Short branch conditional
|
-- 6809 => always 3 cycles
|
-- 6809 => always 3 cycles
|
| Line 2429... |
Line 2007... |
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
|
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
|
-- 3 if cc tru pc=pc+md else pc=pc
|
-- 3 if cc tru pc=pc+md else pc=pc
|
--
|
--
|
when "0010" => -- branch conditional
|
when "0010" => -- branch conditional
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
next_state <= sbranch_state;
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= sbranch_state;
|
|
--
|
--
|
-- Single byte stack operators
|
-- Single byte stack operators
|
-- Do not advance PC
|
-- Do not advance PC
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
--
|
--
|
-- lea - load effective address (2+ bytes)
|
-- lea - load effective address (2+ bytes)
|
-- 6809 => 4 cycles + addressing mode
|
-- 6809 => 4 cycles + addressing mode
|
-- cpu09 => 4 cycles + addressing mode
|
-- cpu09 => 4 cycles + addressing mode
|
-- 1 op=(pc) / pc=pc+1
|
-- 1 op=(pc) / pc=pc+1
|
| Line 2470... |
Line 2029... |
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" | -- leax
|
when "0000" | -- leax
|
"0001" | -- leay
|
"0001" | -- leay
|
"0010" | -- leas
|
"0010" | -- leas
|
"0011" => -- leau
|
"0011" => -- leau
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= lea_state;
|
return_state <= lea_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
--
|
--
|
| Line 2515... |
Line 2063... |
-- 14 if ea(1) = 1 (sp)=acca
|
-- 14 if ea(1) = 1 (sp)=acca
|
-- if ea(0 downto 0) != "0" then sp=sp-1
|
-- if ea(0 downto 0) != "0" then sp=sp-1
|
-- 15 if ea(0) = 1 (sp)=cc
|
-- 15 if ea(0) = 1 (sp)=cc
|
--
|
--
|
when "0100" => -- pshs
|
when "0100" => -- pshs
|
--
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshs_state;
|
next_state <= pshs_state;
|
|
|
--
|
--
|
-- puls - pull registers of sp stack
|
-- puls - pull registers of sp stack
|
-- 6809 => 5 cycles + registers
|
-- 6809 => 5 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
--
|
--
|
when "0101" => -- puls
|
when "0101" => -- puls
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= puls_state;
|
next_state <= puls_state;
|
|
|
--
|
--
|
-- pshu - push registers onto up stack
|
-- pshu - push registers onto up stack
|
-- 6809 => 5 cycles + registers
|
-- 6809 => 5 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
--
|
--
|
when "0110" => -- pshu
|
when "0110" => -- pshu
|
-- idle UP
|
|
left_ctrl <= up_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshu_state;
|
next_state <= pshu_state;
|
|
|
--
|
--
|
-- pulu - pull registers of up stack
|
-- pulu - pull registers of up stack
|
-- 6809 => 5 cycles + registers
|
-- 6809 => 5 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
-- cpu09 => 3 cycles + registers
|
--
|
--
|
when "0111" => -- pulu
|
when "0111" => -- pulu
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- advance PC
|
-- advance PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pulu_state;
|
next_state <= pulu_state;
|
|
|
--
|
--
|
-- rts - return from subroutine
|
-- rts - return from subroutine
|
-- 6809 => 5 cycles
|
-- 6809 => 5 cycles
|
| Line 2613... |
Line 2107... |
-- 2 decode op
|
-- 2 decode op
|
-- 3 pc_hi = (sp) / sp=sp+1
|
-- 3 pc_hi = (sp) / sp=sp+1
|
-- 4 pc_lo = (sp) / sp=sp+1
|
-- 4 pc_lo = (sp) / sp=sp+1
|
--
|
--
|
when "1001" =>
|
when "1001" =>
|
left_ctrl <= sp_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- idle PC
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= pull_return_hi_state;
|
next_state <= pull_return_hi_state;
|
|
|
--
|
--
|
| Line 2643... |
Line 2124... |
--
|
--
|
when "1010" => -- abx
|
when "1010" => -- abx
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= accb_right;
|
right_ctrl <= accb_right;
|
alu_ctrl <= alu_abx;
|
alu_ctrl <= alu_abx;
|
cc_ctrl <= latch_cc;
|
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
--
|
|
pc_ctrl <= latch_pc;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when "1011" => -- rti
|
when "1011" => -- rti
|
-- idle ALU
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
--
|
|
pc_ctrl <= latch_pc;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_cc_state;
|
next_state <= rti_cc_state;
|
|
|
when "1100" => -- cwai #$<cc_mask>
|
when "1100" => -- cwai #$<cc_mask>
|
-- pre decrement sp
|
-- pre decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
--
|
iv_ctrl <= reset_iv;
|
|
-- increment pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= int_entire_state; -- set entire flag
|
return_state <= int_entire_state; -- set entire flag
|
next_state <= andcc_state;
|
next_state <= andcc_state;
|
|
|
when "1101" => -- mul
|
when "1101" => -- mul
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
--
|
|
pc_ctrl <= latch_pc;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul_state;
|
next_state <= mul_state;
|
|
|
when "1111" => -- swi
|
when "1111" => -- swi
|
-- predecrement SP
|
-- predecrement SP
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
--
|
|
pc_ctrl <= latch_pc;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= swi_iv;
|
iv_ctrl <= swi_iv;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
|
|
when others =>
|
when others =>
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- idle PC
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
--
|
--
|
-- Accumulator A Single operand
|
-- Accumulator A Single operand
|
| Line 2759... |
Line 2171... |
-- Note that there is no post byte
|
-- Note that there is no post byte
|
-- so do not advance PC in decode cycle
|
-- so do not advance PC in decode cycle
|
-- Re-run opcode fetch cycle after decode
|
-- Re-run opcode fetch cycle after decode
|
--
|
--
|
when "0100" => -- acca single op
|
when "0100" => -- acca single op
|
op_ctrl <= latch_op;
|
|
accb_ctrl <= latch_accb;
|
|
pc_ctrl <= latch_pc;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- neg
|
when "0000" => -- neg
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_neg;
|
alu_ctrl <= alu_neg;
|
| Line 2840... |
Line 2244... |
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
acca_ctrl <= latch_acca;
|
acca_ctrl <= latch_acca;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
end case;
|
end case;
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
--
|
--
|
-- Single Operand accb
|
-- Single Operand accb
|
-- source = accb, dest = accb
|
-- source = accb, dest = accb
|
-- Typically 2 cycles 1 bytes
|
-- Typically 2 cycles 1 bytes
|
| Line 2854... |
Line 2256... |
-- Note that there is no post byte
|
-- Note that there is no post byte
|
-- so do not advance PC in decode cycle
|
-- so do not advance PC in decode cycle
|
-- Re-run opcode fetch cycle after decode
|
-- Re-run opcode fetch cycle after decode
|
--
|
--
|
when "0101" =>
|
when "0101" =>
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
pc_ctrl <= latch_pc;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- neg
|
when "0000" => -- neg
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_neg;
|
alu_ctrl <= alu_neg;
|
| Line 2935... |
Line 2329... |
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
accb_ctrl <= latch_accb;
|
accb_ctrl <= latch_accb;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
end case;
|
end case;
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
--
|
--
|
-- Single operand indexed
|
-- Single operand indexed
|
-- Two byte instruction so advance PC
|
-- Two byte instruction so advance PC
|
-- EA should hold index offset
|
-- EA should hold index offset
|
--
|
--
|
when "0110" => -- indexed single op
|
when "0110" => -- indexed single op
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- next state
|
st_ctrl <= push_st;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
return_state <= single_op_exec_state;
|
return_state <= single_op_exec_state;
|
when others =>
|
when others =>
|
return_state <= single_op_read_state;
|
return_state <= single_op_read_state;
|
end case;
|
end case;
|
st_ctrl <= push_st;
|
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
--
|
--
|
-- Single operand extended addressing
|
-- Single operand extended addressing
|
-- three byte instruction so advance the PC
|
-- three byte instruction so advance the PC
|
-- Low order EA holds high order address
|
-- Low order EA holds high order address
|
--
|
--
|
when "0111" => -- extended single op
|
when "0111" => -- extended single op
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment PC
|
-- increment PC
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
st_ctrl <= push_st;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
return_state <= single_op_exec_state;
|
return_state <= single_op_exec_state;
|
when others =>
|
when others =>
|
return_state <= single_op_read_state;
|
return_state <= single_op_read_state;
|
end case;
|
end case;
|
st_ctrl <= push_st;
|
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1000" => -- acca immediate
|
when "1000" => -- acca immediate
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd #
|
when "0011" | -- subd #
|
"1100" | -- cmpx #
|
"1100" | -- cmpx #
|
"1110" => -- ldx #
|
"1110" => -- ldx #
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
--
|
--
|
| Line 3043... |
Line 2393... |
when "1101" => -- bsr
|
when "1101" => -- bsr
|
-- pre decrement SP
|
-- pre decrement SP
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
--
|
--
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= sbranch_state;
|
return_state <= sbranch_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
|
|
when others =>
|
when others =>
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1001" => -- acca direct
|
when "1001" => -- acca direct
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd
|
when "0011" | -- subd
|
"1100" | -- cmpx
|
"1100" | -- cmpx
|
"1110" => -- ldx
|
"1110" => -- ldx
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "0111" => -- sta direct
|
when "0111" => -- sta direct
|
-- idle ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write8_state;
|
next_state <= dual_op_write8_state;
|
|
|
when "1111" => -- stx direct
|
when "1111" => -- stx direct
|
-- idle ALU
|
-- idle ALU
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_nop;
|
cc_ctrl <= latch_cc;
|
cc_ctrl <= latch_cc;
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
--
|
--
|
-- jsr direct - Jump to subroutine in direct page (2 bytes)
|
-- jsr direct - Jump to subroutine in direct page (2 bytes)
|
-- 6809 => 7 cycles
|
-- 6809 => 7 cycles
|
| Line 3127... |
Line 2439... |
when "1101" => -- jsr direct
|
when "1101" => -- jsr direct
|
-- pre decrement sp
|
-- pre decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
--
|
--
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
|
|
when others =>
|
when others =>
|
-- idle ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_read8_state;
|
next_state <= dual_op_read8_state;
|
end case;
|
end case;
|
|
|
when "1010" => -- acca indexed
|
when "1010" => -- acca indexed
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd
|
when "0011" | -- subd
|
"1100" | -- cmpx
|
"1100" | -- cmpx
|
"1110" => -- ldx
|
"1110" => -- ldx
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "0111" => -- staa ,x
|
when "0111" => -- staa ,x
|
-- idle ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write8_state;
|
return_state <= dual_op_write8_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1111" => -- stx ,x
|
when "1111" => -- stx ,x
|
-- idle ALU
|
|
left_ctrl <= ix_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when "1101" => -- jsr ,x
|
when "1101" => -- jsr ,x
|
-- DO NOT pre decrement SP
|
-- DO NOT pre decrement SP
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_sub16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jsr_state;
|
return_state <= jsr_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read8_state;
|
return_state <= dual_op_read8_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
end case;
|
end case;
|
|
|
when "1011" => -- acca extended
|
when "1011" => -- acca extended
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- subd
|
when "0011" | -- subd
|
"1100" | -- cmpx
|
"1100" | -- cmpx
|
"1110" => -- ldx
|
"1110" => -- ldx
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "0111" => -- staa >
|
when "0111" => -- staa >
|
-- idle ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write8_state;
|
return_state <= dual_op_write8_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1111" => -- stx >
|
when "1111" => -- stx >
|
-- idle ALU
|
|
left_ctrl <= ix_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when "1101" => -- jsr >extended
|
when "1101" => -- jsr >extended
|
-- DO NOT pre decrement sp
|
-- DO NOT pre decrement sp
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_sub16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jsr_state;
|
return_state <= jsr_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when others =>
|
when others =>
|
-- idle ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_st8;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read8_state;
|
return_state <= dual_op_read8_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
end case;
|
end case;
|
|
|
when "1100" => -- accb immediate
|
when "1100" => -- accb immediate
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd #
|
when "0011" | -- addd #
|
"1100" | -- ldd #
|
"1100" | -- ldd #
|
| Line 3320... |
Line 2527... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
|
|
when "1101" => -- accb direct
|
when "1101" => -- accb direct
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
--
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd
|
when "0011" | -- addd
|
"1100" | -- ldd
|
"1100" | -- ldd
|
"1110" => -- ldu
|
"1110" => -- ldu
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "0111" => -- stab direct
|
when "0111" => -- stab direct
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write8_state;
|
next_state <= dual_op_write8_state;
|
|
|
when "1101" => -- std direct
|
when "1101" => -- std direct
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when "1111" => -- stu direct
|
when "1111" => -- stu direct
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_read8_state;
|
next_state <= dual_op_read8_state;
|
end case;
|
end case;
|
|
|
when "1110" => -- accb indexed
|
when "1110" => -- accb indexed
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
--
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd
|
when "0011" | -- addd
|
"1100" | -- ldd
|
"1100" | -- ldd
|
"1110" => -- ldu
|
"1110" => -- ldu
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
| Line 3420... |
Line 2587... |
return_state <= dual_op_read8_state;
|
return_state <= dual_op_read8_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
end case;
|
end case;
|
|
|
when "1111" => -- accb extended
|
when "1111" => -- accb extended
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
--
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- addd
|
when "0011" | -- addd
|
"1100" | -- ldd
|
"1100" | -- ldd
|
"1110" => -- ldu
|
"1110" => -- ldu
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
| Line 3467... |
Line 2620... |
next_state <= extended_state;
|
next_state <= extended_state;
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
-- op_ctrl <= latch_op;
|
|
-- acca_ctrl <= latch_acca;
|
|
-- accb_ctrl <= latch_accb;
|
|
-- ix_ctrl <= latch_ix;
|
|
-- iy_ctrl <= latch_iy;
|
|
-- up_ctrl <= latch_up;
|
|
-- sp_ctrl <= latch_sp;
|
|
-- iv_ctrl <= latch_iv;
|
|
-- -- idle the ALU
|
|
-- left_ctrl <= pc_left;
|
|
-- right_ctrl <= zero_right;
|
|
-- alu_ctrl <= alu_nop;
|
|
-- cc_ctrl <= latch_cc;
|
|
-- -- idle the pc
|
|
-- pc_ctrl <= latch_pc;
|
|
-- --
|
|
-- st_ctrl <= idle_st;
|
|
-- return_state <= fetch_state;
|
|
-- next_state <= fetch_state;
|
|
end case;
|
end case;
|
|
|
--
|
--
|
-- Here to decode prefix 2 instruction
|
-- Here to decode prefix 2 instruction
|
-- and fetch next byte of intruction
|
-- and fetch next byte of intruction
|
-- whether it be necessary or not
|
-- whether it be necessary or not
|
--
|
--
|
when decode2_state =>
|
when decode2_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
-- fetch first byte of address or immediate data
|
-- fetch first byte of address or immediate data
|
ea_ctrl <= fetch_first_ea;
|
ea_ctrl <= fetch_first_ea;
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
nmi_ctrl <= latch_nmi;
|
|
dp_ctrl <= latch_dp;
|
|
case op_code(7 downto 4) is
|
case op_code(7 downto 4) is
|
--
|
--
|
-- lbcc -- long branch conditional
|
-- lbcc -- long branch conditional
|
-- 6809 => branch 6 cycles, no branch 5 cycles
|
-- 6809 => branch 6 cycles, no branch 5 cycles
|
-- cpu09 => always 5 cycles
|
-- cpu09 => always 5 cycles
|
| Line 3515... |
Line 2644... |
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
|
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
|
-- 5 if cond pc=pc+md else pc=pc
|
-- 5 if cond pc=pc+md else pc=pc
|
--
|
--
|
when "0010" =>
|
when "0010" =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
-- increment the pc
|
-- increment the pc
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= lbranch_state;
|
next_state <= lbranch_state;
|
|
|
--
|
--
|
-- Single byte stack operators
|
-- Single byte stack operators
|
-- Do not advance PC
|
-- Do not advance PC
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1111" => -- swi 2
|
when "1111" => -- swi 2
|
-- predecrement sp
|
-- predecrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
iv_ctrl <= swi2_iv;
|
iv_ctrl <= swi2_iv;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
|
|
when others =>
|
when others =>
|
left_ctrl <= sp_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1000" => -- acca immediate
|
when "1000" => -- acca immediate
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- Idle the ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd #
|
when "0011" | -- cmpd #
|
"1100" | -- cmpy #
|
"1100" | -- cmpy #
|
| Line 3595... |
Line 2679... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1001" => -- acca direct
|
when "1001" => -- acca direct
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd <
|
when "0011" | -- cmpd <
|
"1100" | -- cmpy <
|
"1100" | -- cmpy <
|
"1110" => -- ldy <
|
"1110" => -- ldy <
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "1111" => -- sty <
|
when "1111" => -- sty <
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1010" => -- acca indexed
|
when "1010" => -- acca indexed
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd ,ind
|
when "0011" | -- cmpd ,ind
|
"1100" | -- cmpy ,ind
|
"1100" | -- cmpy ,ind
|
| Line 3665... |
Line 2717... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1011" => -- acca extended
|
when "1011" => -- acca extended
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpd <
|
when "0011" | -- cmpd <
|
"1100" | -- cmpy <
|
"1100" | -- cmpy <
|
| Line 3699... |
Line 2737... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1100" => -- accb immediate
|
when "1100" => -- accb immediate
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef #
|
when "0011" | -- undef #
|
"1100" | -- undef #
|
"1100" | -- undef #
|
| Line 3729... |
Line 2753... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1101" => -- accb direct
|
when "1101" => -- accb direct
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef <
|
when "0011" | -- undef <
|
"1100" | -- undef <
|
"1100" | -- undef <
|
"1110" => -- lds <
|
"1110" => -- lds <
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when "1111" => -- sts <
|
when "1111" => -- sts <
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write16_state;
|
next_state <= dual_op_write16_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1110" => -- accb indexed
|
when "1110" => -- accb indexed
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef ,ind
|
when "0011" | -- undef ,ind
|
"1100" | -- undef ,ind
|
"1100" | -- undef ,ind
|
| Line 3799... |
Line 2791... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1111" => -- accb extended
|
when "1111" => -- accb extended
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- undef >
|
when "0011" | -- undef >
|
"1100" | -- undef >
|
"1100" | -- undef >
|
| Line 3834... |
Line 2812... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_write16_state;
|
return_state <= dual_op_write16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- idle the pc
|
|
pc_ctrl <= latch_pc;
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
--
|
--
|
-- Here to decode instruction
|
-- Here to decode instruction
|
-- and fetch next byte of intruction
|
-- and fetch next byte of intruction
|
-- whether it be necessary or not
|
-- whether it be necessary or not
|
--
|
--
|
when decode3_state =>
|
when decode3_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
ea_ctrl <= fetch_first_ea;
|
ea_ctrl <= fetch_first_ea;
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
nmi_ctrl <= latch_nmi;
|
|
dp_ctrl <= latch_dp;
|
|
case op_code(7 downto 4) is
|
case op_code(7 downto 4) is
|
--
|
--
|
-- Single byte stack operators
|
-- Single byte stack operators
|
-- Do not advance PC
|
-- Do not advance PC
|
--
|
--
|
when "0011" =>
|
when "0011" =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "1111" => -- swi3
|
when "1111" => -- swi3
|
-- predecrement sp
|
-- predecrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
iv_ctrl <= swi3_iv;
|
iv_ctrl <= swi3_iv;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
when others =>
|
when others =>
|
left_ctrl <= sp_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1000" => -- acca immediate
|
when "1000" => -- acca immediate
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu #
|
when "0011" | -- cmpu #
|
"1100" | -- cmps #
|
"1100" | -- cmps #
|
"1110" => -- undef #
|
"1110" => -- undef #
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= imm16_state;
|
next_state <= imm16_state;
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when "1001" => -- acca direct
|
when "1001" => -- acca direct
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu <
|
when "0011" | -- cmpu <
|
"1100" | -- cmps <
|
"1100" | -- cmps <
|
| Line 3964... |
Line 2873... |
st_ctrl <= idle_st;
|
st_ctrl <= idle_st;
|
return_state <= fetch_state;
|
return_state <= fetch_state;
|
next_state <= dual_op_read16_state;
|
next_state <= dual_op_read16_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1010" => -- acca indexed
|
when "1010" => -- acca indexed
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu ,X
|
when "0011" | -- cmpu ,X
|
"1100" | -- cmps ,X
|
"1100" | -- cmps ,X
|
| Line 3994... |
Line 2889... |
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= indexed_state;
|
next_state <= indexed_state;
|
|
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
end case;
|
end case;
|
|
|
when "1011" => -- acca extended
|
when "1011" => -- acca extended
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- increment the pc
|
-- increment the pc
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0011" | -- cmpu >
|
when "0011" | -- cmpu >
|
"1100" | -- cmps >
|
"1100" | -- cmps >
|
"1110" => -- undef >
|
"1110" => -- undef >
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= dual_op_read16_state;
|
return_state <= dual_op_read16_state;
|
next_state <= extended_state;
|
next_state <= extended_state;
|
when others =>
|
when others =>
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
-- idle the alu
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- idle the pc
|
|
pc_ctrl <= latch_pc;
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- here if ea holds low byte
|
-- here if ea holds low byte
|
| Line 4056... |
Line 2919... |
-- Extended
|
-- Extended
|
-- Indexed
|
-- Indexed
|
-- read memory location
|
-- read memory location
|
--
|
--
|
when single_op_read_state =>
|
when single_op_read_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
nmi_ctrl <= latch_nmi;
|
|
-- idle ALU
|
|
left_ctrl <= ea_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
-- read memory into md
|
-- read memory into md
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= single_op_exec_state;
|
next_state <= single_op_exec_state;
|
|
|
when single_op_exec_state =>
|
when single_op_exec_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
dp_ctrl <= latch_dp;
|
|
nmi_ctrl <= latch_nmi;
|
|
iv_ctrl <= latch_iv;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle the bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- neg
|
when "0000" => -- neg
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_neg;
|
alu_ctrl <= alu_neg;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0011" => -- com
|
when "0011" => -- com
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_com;
|
alu_ctrl <= alu_com;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0100" => -- lsr
|
when "0100" => -- lsr
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_lsr8;
|
alu_ctrl <= alu_lsr8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0110" => -- ror
|
when "0110" => -- ror
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ror8;
|
alu_ctrl <= alu_ror8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "0111" => -- asr
|
when "0111" => -- asr
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asr8;
|
alu_ctrl <= alu_asr8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1000" => -- asl
|
when "1000" => -- asl
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_asl8;
|
alu_ctrl <= alu_asl8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1001" => -- rol
|
when "1001" => -- rol
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_rol8;
|
alu_ctrl <= alu_rol8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1010" => -- dec
|
when "1010" => -- dec
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_dec;
|
alu_ctrl <= alu_dec;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1011" => -- undefined
|
when "1011" => -- undefined
|
left_ctrl <= md_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
md_ctrl <= latch_md;
|
|
pc_ctrl <= latch_pc;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
when "1100" => -- inc
|
when "1100" => -- inc
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_inc;
|
alu_ctrl <= alu_inc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when "1101" => -- tst
|
when "1101" => -- tst
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st8;
|
alu_ctrl <= alu_st8;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= latch_md;
|
|
pc_ctrl <= latch_pc;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
when "1110" => -- jmp
|
when "1110" => -- jmp
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
cc_ctrl <= latch_cc;
|
|
md_ctrl <= latch_md;
|
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
when "1111" => -- clr
|
when "1111" => -- clr
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_clr;
|
alu_ctrl <= alu_clr;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
pc_ctrl <= latch_pc;
|
|
next_state <= single_op_write_state;
|
next_state <= single_op_write_state;
|
when others =>
|
when others =>
|
left_ctrl <= md_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
md_ctrl <= latch_md;
|
|
pc_ctrl <= latch_pc;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end case;
|
end case;
|
--
|
--
|
-- single operand 8 bit write
|
-- single operand 8 bit write
|
-- Write low 8 bits of ALU output
|
-- Write low 8 bits of ALU output
|
-- EA holds address
|
-- EA holds address
|
-- MD holds data
|
-- MD holds data
|
--
|
--
|
when single_op_write_state =>
|
when single_op_write_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle the ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
-- write ALU low byte output
|
-- write ALU low byte output
|
addr_ctrl <= write_ad;
|
addr_ctrl <= write_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- here if ea holds address of low byte
|
-- here if ea holds address of low byte
|
-- read memory location
|
-- read memory location
|
--
|
--
|
when dual_op_read8_state =>
|
when dual_op_read8_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
nmi_ctrl <= latch_nmi;
|
|
left_ctrl <= ea_left;
|
|
-- Leave the ea alone
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
-- read first data byte from ea
|
-- read first data byte from ea
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- Here to read a 16 bit value into MD
|
-- Here to read a 16 bit value into MD
|
-- pointed to by the EA register
|
-- pointed to by the EA register
|
-- The first byte is read
|
-- The first byte is read
|
-- and the EA is incremented
|
-- and the EA is incremented
|
--
|
--
|
when dual_op_read16_state =>
|
when dual_op_read16_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
-- increment the effective address
|
-- increment the effective address
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- read the low byte of the 16 bit data
|
-- read the high byte of the 16 bit data
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_read16_2_state;
|
next_state <= dual_op_read16_2_state;
|
|
|
--
|
--
|
-- here to read the second byte
|
-- here to read the second byte
|
-- pointed to by EA into MD
|
-- pointed to by EA into MD
|
--
|
--
|
when dual_op_read16_2_state =>
|
when dual_op_read16_2_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
-- idle the effective address
|
|
left_ctrl <= ea_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_nop;
|
|
ea_ctrl <= latch_ea;
|
|
-- read the low byte of the 16 bit data
|
-- read the low byte of the 16 bit data
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- 16 bit Write state
|
-- 16 bit Write state
|
-- EA hold address of memory to write to
|
-- EA hold address of memory to write to
|
-- Advance the effective address in ALU
|
-- Advance the effective address in ALU
|
-- decode op_code to determine which
|
-- decode op_code to determine which
|
-- register to write
|
-- register to write
|
--
|
--
|
when dual_op_write16_state =>
|
when dual_op_write16_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
nmi_ctrl <= latch_nmi;
|
|
-- increment the effective address
|
-- increment the effective address
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- write the ALU hi byte at ea
|
-- write the ALU hi byte at ea
|
addr_ctrl <= write_ad;
|
addr_ctrl <= write_ad;
|
if op_code(6) = '0' then
|
if op_code(6) = '0' then
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
| Line 4403... |
Line 3105... |
end case;
|
end case;
|
when others =>
|
when others =>
|
dout_ctrl <= md_hi_dout;
|
dout_ctrl <= md_hi_dout;
|
end case;
|
end case;
|
end if;
|
end if;
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= dual_op_write8_state;
|
next_state <= dual_op_write8_state;
|
|
|
--
|
--
|
-- Dual operand 8 bit write
|
-- Dual operand 8 bit write
|
-- Write 8 bit accumulator
|
-- Write 8 bit accumulator
|
| Line 4417... |
Line 3117... |
-- decode opcode to determine
|
-- decode opcode to determine
|
-- which register to apply to the bus
|
-- which register to apply to the bus
|
-- Also set the condition codes here
|
-- Also set the condition codes here
|
--
|
--
|
when dual_op_write8_state =>
|
when dual_op_write8_state =>
|
op_ctrl <= latch_op;
|
if op_code(6) = '0' then
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
nmi_ctrl <= latch_nmi;
|
|
md_ctrl <= latch_md;
|
|
-- idle ALU
|
|
left_ctrl <= ea_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
|
if op_code(6) = '0' then -- '0' = acca line
|
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0111" => -- sta
|
when "0111" => -- sta
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
when "1111" => -- stx / sty
|
when "1111" => -- stx / sty
|
case pre_code is
|
case pre_code is
|
| Line 4451... |
Line 3131... |
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
end case;
|
end case;
|
when others =>
|
when others =>
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
end case;
|
end case;
|
else -- '1' = accb line
|
else
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0111" => -- stb
|
when "0111" => -- stb
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
when "1101" => -- std
|
when "1101" => -- std
|
dout_ctrl <= accb_dout; -- accb is low byte of accd
|
dout_ctrl <= accb_dout; -- accb is low byte of accd
|
| Line 4470... |
Line 3150... |
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
end case;
|
end case;
|
end if;
|
end if;
|
-- write ALU low byte output
|
-- write ALU low byte output
|
addr_ctrl <= write_ad;
|
addr_ctrl <= write_ad;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- 16 bit immediate addressing mode
|
-- 16 bit immediate addressing mode
|
--
|
--
|
when imm16_state =>
|
when imm16_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
--
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment pc
|
-- increment pc
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch next immediate byte
|
-- fetch next immediate byte
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
-- return to caller
|
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
--
|
--
|
-- md & ea holds 8 bit index offset
|
-- md & ea holds 8 bit index offset
|
-- calculate the effective memory address
|
-- calculate the effective memory address
|
-- using the alu
|
-- using the alu
|
--
|
--
|
when indexed_state =>
|
when indexed_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
nmi_ctrl <= latch_nmi;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
--
|
-- decode indexing mode
|
-- decode indexing mode
|
--
|
--
|
if md(7) = '0' then
|
if md(7) = '0' then
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4543... |
Line 3187... |
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= md_sign5_right;
|
right_ctrl <= md_sign5_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
else
|
else
|
case md(3 downto 0) is
|
case md(3 downto 0) is
|
when "0000" => -- ,R+
|
when "0000" => -- ,R+
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4573... |
Line 3206... |
when others =>
|
when others =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
--
|
--
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= postincr1_state;
|
next_state <= postincr1_state;
|
|
|
when "0001" => -- ,R++
|
when "0001" => -- ,R++
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4602... |
Line 3223... |
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= postincr2_state;
|
next_state <= postincr2_state;
|
|
|
when "0010" => -- ,-R
|
when "0010" => -- ,-R
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when "0011" => -- ,--R
|
when "0011" => -- ,--R
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "10" =>
|
when "10" =>
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
right_ctrl <= two_right;
|
right_ctrl <= two_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0100" => -- ,R (zero offset)
|
when "0100" => -- ,R (zero offset)
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4719... |
Line 3288... |
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0101" => -- ACCB,R
|
when "0101" => -- ACCB,R
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4755... |
Line 3311... |
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= accb_right;
|
right_ctrl <= accb_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0110" => -- ACCA,R
|
when "0110" => -- ACCA,R
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4790... |
Line 3333... |
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= acca_right;
|
right_ctrl <= acca_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "0111" => -- undefined
|
when "0111" => -- undefined
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4824... |
Line 3354... |
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= latch_ea;
|
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "1000" => -- offset8,R
|
when "1000" => -- offset8,R
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
|
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
|
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= index8_state;
|
next_state <= index8_state;
|
|
|
when "1001" => -- offset16,R
|
when "1001" => -- offset16,R
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
|
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
|
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= index16_state;
|
next_state <= index16_state;
|
|
|
when "1010" => -- undefined
|
when "1010" => -- undefined
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4899... |
Line 3388... |
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= latch_ea;
|
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
--
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "1011" => -- ACCD,R
|
when "1011" => -- ACCD,R
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 4935... |
Line 3412... |
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= accd_right;
|
right_ctrl <= accd_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when "1100" => -- offset8,PC
|
when "1100" => -- offset8,PC
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
-- fetch 8 bit offset
|
-- fetch 8 bit offset
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pcrel8_state;
|
next_state <= pcrel8_state;
|
|
|
when "1101" => -- offset16,PC
|
when "1101" => -- offset16,PC
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
-- fetch offset
|
-- fetch offset
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pcrel16_state;
|
next_state <= pcrel16_state;
|
|
|
when "1110" => -- undefined
|
when "1110" => -- undefined
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 5009... |
Line 3447... |
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_nop;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
--
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
pc_ctrl <= latch_pc;
|
|
--
|
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
-- when "1111" => -- [,address]
|
-- when "1111" => -- [,address]
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
-- idle ALU
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= latch_ea;
|
|
-- advance PC to pick up address
|
-- advance PC to pick up address
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indexaddr_state;
|
next_state <= indexaddr_state;
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
-- load index register with ea plus one
|
-- load index register with ea plus one
|
when postincr1_state =>
|
when postincr1_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "01" =>
|
when "01" =>
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "10" =>
|
when "10" =>
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- load index register with ea plus two
|
-- load index register with ea plus two
|
when postincr2_state =>
|
when postincr2_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment register by two (address)
|
-- increment register by two (address)
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= two_right;
|
right_ctrl <= two_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
case md(6 downto 5) is
|
case md(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "01" =>
|
when "01" =>
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "10" =>
|
when "10" =>
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
when others =>
|
when others =>
|
-- when "11" =>
|
-- when "11" =>
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end case;
|
end case;
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
if md(4) = '0' then
|
if md(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
--
|
--
|
-- ea = index register + md (8 bit signed offset)
|
-- ea = index register + md (8 bit signed offset)
|
-- ea holds post byte
|
-- ea holds post byte
|
--
|
--
|
when index8_state =>
|
when index8_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
case ea(6 downto 5) is
|
case ea(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 5189... |
Line 3534... |
end case;
|
end case;
|
-- ea = index reg + md
|
-- ea = index reg + md
|
right_ctrl <= md_sign8_right;
|
right_ctrl <= md_sign8_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- fetch low byte of 16 bit indexed offset
|
-- fetch low byte of 16 bit indexed offset
|
when index16_state =>
|
when index16_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
-- advance pc
|
-- advance pc
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch low byte
|
-- fetch low byte
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= index16_2_state;
|
next_state <= index16_2_state;
|
|
|
-- ea = index register + md (16 bit offset)
|
-- ea = index register + md (16 bit offset)
|
-- ea holds post byte
|
-- ea holds post byte
|
when index16_2_state =>
|
when index16_2_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
case ea(6 downto 5) is
|
case ea(6 downto 5) is
|
when "00" =>
|
when "00" =>
|
left_ctrl <= ix_left;
|
left_ctrl <= ix_left;
|
when "01" =>
|
when "01" =>
|
left_ctrl <= iy_left;
|
left_ctrl <= iy_left;
|
| Line 5264... |
Line 3569... |
end case;
|
end case;
|
-- ea = index reg + md
|
-- ea = index reg + md
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
--
|
--
|
-- pc relative with 8 bit signed offest
|
-- pc relative with 8 bit signed offest
|
-- md holds signed offset
|
-- md holds signed offset
|
--
|
--
|
when pcrel8_state =>
|
when pcrel8_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
-- ea = pc + signed md
|
-- ea = pc + signed md
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_sign8_right;
|
right_ctrl <= md_sign8_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- pc relative addressing with 16 bit offset
|
-- pc relative addressing with 16 bit offset
|
-- pick up the low byte of the offset in md
|
-- pick up the low byte of the offset in md
|
-- advance the pc
|
-- advance the pc
|
when pcrel16_state =>
|
when pcrel16_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- advance pc
|
-- advance pc
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch low byte
|
-- fetch low byte
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pcrel16_2_state;
|
next_state <= pcrel16_2_state;
|
|
|
-- pc relative with16 bit signed offest
|
-- pc relative with16 bit signed offest
|
-- md holds signed offset
|
-- md holds signed offset
|
when pcrel16_2_state =>
|
when pcrel16_2_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
-- ea = pc + md
|
-- ea = pc + md
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
md_ctrl <= latch_md;
|
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
-- indexed to address
|
-- indexed to address
|
-- pick up the low byte of the address
|
-- pick up the low byte of the address
|
-- advance the pc
|
-- advance the pc
|
when indexaddr_state =>
|
when indexaddr_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
-- advance pc
|
-- advance pc
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch low byte
|
-- fetch low byte
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indexaddr2_state;
|
next_state <= indexaddr2_state;
|
|
|
-- indexed to absolute address
|
-- indexed to absolute address
|
-- md holds address
|
-- md holds address
|
-- ea hold indexing mode byte
|
-- ea hold indexing mode byte
|
when indexaddr2_state =>
|
when indexaddr2_state =>
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
-- ea = md
|
-- ea = md
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
md_ctrl <= latch_md;
|
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
if ea(4) = '0' then
|
if ea(4) = '0' then
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect_state;
|
next_state <= indirect_state;
|
end if;
|
end if;
|
|
|
--
|
--
|
-- load md with high byte of indirect address
|
-- load md with high byte of indirect address
|
-- pointed to by ea
|
-- pointed to by ea
|
-- increment ea
|
-- increment ea
|
--
|
--
|
when indirect_state =>
|
when indirect_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
-- increment ea
|
-- increment ea
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- fetch high byte
|
-- fetch high byte
|
md_ctrl <= fetch_first_md;
|
md_ctrl <= fetch_first_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect2_state;
|
next_state <= indirect2_state;
|
--
|
--
|
-- load md with low byte of indirect address
|
-- load md with low byte of indirect address
|
-- pointed to by ea
|
-- pointed to by ea
|
-- ea has previously been incremented
|
-- ea has previously been incremented
|
--
|
--
|
when indirect2_state =>
|
when indirect2_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
-- idle ea
|
|
left_ctrl <= ea_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
ea_ctrl <= latch_ea;
|
|
-- fetch high byte
|
-- fetch high byte
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= read_ad;
|
addr_ctrl <= read_ad;
|
dout_ctrl <= md_lo_dout;
|
dout_ctrl <= md_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= indirect3_state;
|
next_state <= indirect3_state;
|
--
|
--
|
-- complete idirect addressing
|
-- complete idirect addressing
|
-- by loading ea with md
|
-- by loading ea with md
|
--
|
--
|
when indirect3_state =>
|
when indirect3_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
pc_ctrl <= latch_pc;
|
|
-- load ea with md
|
-- load ea with md
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- idle cycle
|
|
md_ctrl <= latch_md;
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
--
|
--
|
-- ea holds the low byte of the absolute address
|
-- ea holds the low byte of the absolute address
|
-- Move ea low byte into ea high byte
|
-- Move ea low byte into ea high byte
|
-- load new ea low byte to for absolute 16 bit address
|
-- load new ea low byte to for absolute 16 bit address
|
-- advance the program counter
|
-- advance the program counter
|
--
|
--
|
when extended_state => -- fetch ea low byte
|
when extended_state => -- fetch ea low byte
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
-- increment pc
|
-- increment pc
|
left_ctrl <= pc_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch next effective address bytes
|
-- fetch next effective address bytes
|
ea_ctrl <= fetch_next_ea;
|
ea_ctrl <= fetch_next_ea;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
-- return to previous state
|
-- return to previous state
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when lea_state => -- here on load effective address
|
when lea_state => -- here on load effective address
|
op_ctrl <= latch_op;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iv_ctrl <= latch_iv;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
md_ctrl <= latch_md;
|
|
ea_ctrl <= latch_ea;
|
|
pc_ctrl <= latch_pc;
|
|
-- load index register with effective address
|
-- load index register with effective address
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= ea_right;
|
right_ctrl <= ea_right;
|
alu_ctrl <= alu_lea;
|
alu_ctrl <= alu_lea;
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- leax
|
when "0000" => -- leax
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0001" => -- leay
|
when "0001" => -- leay
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
when "0010" => -- leas
|
when "0010" => -- leas
|
cc_ctrl <= latch_cc;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
when "0011" => -- leau
|
when "0011" => -- leau
|
cc_ctrl <= latch_cc;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
when others =>
|
when others =>
|
cc_ctrl <= latch_cc;
|
null;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
end case;
|
end case;
|
-- idle the bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- jump to subroutine
|
-- jump to subroutine
|
-- sp=sp-1
|
-- sp=sp-1
|
-- call push_return_lo_state to save pc
|
-- call push_return_lo_state to save pc
|
-- return to jmp_state
|
-- return to jmp_state
|
--
|
--
|
when jsr_state =>
|
when jsr_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
md_ctrl <= latch_md;
|
|
ea_ctrl <= latch_ea;
|
|
pc_ctrl <= latch_pc;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= pc_lo_dout;
|
|
-- call push_return_state
|
-- call push_return_state
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= jmp_state;
|
return_state <= jmp_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
|
|
--
|
--
|
-- Load pc with ea
|
-- Load pc with ea
|
-- (JMP)
|
-- (JMP)
|
--
|
--
|
when jmp_state =>
|
when jmp_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
md_ctrl <= latch_md;
|
|
ea_ctrl <= latch_ea;
|
|
-- load PC with effective address
|
-- load PC with effective address
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= ea_right;
|
right_ctrl <= ea_right;
|
alu_ctrl <= alu_ld16;
|
alu_ctrl <= alu_ld16;
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
-- idle the bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- long branch or branch to subroutine
|
-- long branch or branch to subroutine
|
-- pick up next md byte
|
-- pick up next md byte
|
| Line 5713... |
Line 3766... |
-- if a lbsr push return address
|
-- if a lbsr push return address
|
-- continue to sbranch_state
|
-- continue to sbranch_state
|
-- to evaluate conditional branches
|
-- to evaluate conditional branches
|
--
|
--
|
when lbranch_state =>
|
when lbranch_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= ea_right;
|
|
alu_ctrl <= alu_ld16;
|
|
pc_ctrl <= incr_pc;
|
pc_ctrl <= incr_pc;
|
-- fetch the next byte into md_lo
|
-- fetch the next byte into md_lo
|
md_ctrl <= fetch_next_md;
|
md_ctrl <= fetch_next_md;
|
addr_ctrl <= fetch_ad;
|
addr_ctrl <= fetch_ad;
|
dout_ctrl <= md_lo_dout;
|
|
-- if lbsr - push return address
|
-- if lbsr - push return address
|
-- then continue on to short branch
|
-- then continue on to short branch
|
if op_code = "00010111" then
|
if op_code = "00010111" then
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= sbranch_state;
|
return_state <= sbranch_state;
|
next_state <= push_return_lo_state;
|
next_state <= push_return_lo_state;
|
else
|
else
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= sbranch_state;
|
next_state <= sbranch_state;
|
end if;
|
end if;
|
|
|
--
|
--
|
-- here to execute conditional branch
|
-- here to execute conditional branch
|
-- short conditional branch md = signed 8 bit offset
|
-- short conditional branch md = signed 8 bit offset
|
-- long branch md = 16 bit offset
|
-- long branch md = 16 bit offset
|
--
|
--
|
when sbranch_state =>
|
when sbranch_state =>
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= latch_md;
|
|
--
|
|
left_ctrl <= pc_left;
|
left_ctrl <= pc_left;
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
--
|
-- Test condition for branch
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
|
if op_code(7 downto 4) = "0010" then -- conditional branch
|
if op_code(7 downto 4) = "0010" then -- conditional branch
|
case op_code(3 downto 0) is
|
case op_code(3 downto 0) is
|
when "0000" => -- bra
|
when "0000" => -- bra
|
cond_true := (1 = 1);
|
cond_true := (1 = 1);
|
when "0001" => -- brn
|
when "0001" => -- brn
|
| Line 5814... |
Line 3826... |
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
|
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
|
when "1111" => -- ble
|
when "1111" => -- ble
|
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
|
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
|
when others =>
|
when others =>
|
null;
|
null;
|
-- cond_true := (1 = 1);
|
|
end case;
|
end case;
|
else
|
else
|
cond_true := (1 = 1); -- lbra, lbsr, bsr
|
cond_true := (1 = 1); -- lbra, lbsr, bsr
|
end if;
|
end if;
|
if cond_true then
|
if cond_true then
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
else
|
|
pc_ctrl <= latch_pc;
|
|
end if;
|
end if;
|
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- push return address onto the S stack
|
-- push return address onto the S stack
|
--
|
--
|
-- (sp) = pc_lo
|
-- (sp) = pc_lo
|
-- sp = sp - 1
|
-- sp = sp - 1
|
--
|
--
|
when push_return_lo_state =>
|
when push_return_lo_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement the sp
|
-- decrement the sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write PC low
|
-- write PC low
|
pc_ctrl <= latch_pc;
|
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= push_return_hi_state;
|
next_state <= push_return_hi_state;
|
|
|
--
|
--
|
-- push program counter hi byte onto the stack
|
-- push program counter hi byte onto the stack
|
-- (sp) = pc_hi
|
-- (sp) = pc_hi
|
-- sp = sp
|
-- sp = sp
|
-- return to originating state
|
-- return to originating state
|
--
|
--
|
when push_return_hi_state =>
|
when push_return_hi_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle the SP
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_sub16;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- write pc hi bytes
|
-- write pc hi bytes
|
pc_ctrl <= latch_pc;
|
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
--
|
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when pull_return_hi_state =>
|
when pull_return_hi_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment the sp
|
-- increment the sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read pc hi
|
-- read pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= pc_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pull_return_lo_state;
|
next_state <= pull_return_lo_state;
|
|
|
when pull_return_lo_state =>
|
when pull_return_lo_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment the SP
|
-- increment the SP
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read pc low
|
-- read pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when andcc_state =>
|
when andcc_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= latch_md;
|
|
-- AND CC with md
|
-- AND CC with md
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_andcc;
|
alu_ctrl <= alu_andcc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when orcc_state =>
|
when orcc_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= latch_md;
|
|
-- OR CC with md
|
-- OR CC with md
|
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_orcc;
|
alu_ctrl <= alu_orcc;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when tfr_state =>
|
when tfr_state =>
|
-- default
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= latch_md;
|
|
-- select source register
|
-- select source register
|
case md(7 downto 4) is
|
case md(7 downto 4) is
|
when "0000" =>
|
when "0000" =>
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
when "0001" =>
|
when "0001" =>
|
| Line 6049... |
Line 3941... |
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_tfr;
|
alu_ctrl <= alu_tfr;
|
-- select destination register
|
-- select destination register
|
case md(3 downto 0) is
|
case md(3 downto 0) is
|
when "0000" => -- accd
|
when "0000" => -- accd
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0001" => -- ix
|
when "0001" => -- ix
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0010" => -- iy
|
when "0010" => -- iy
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0011" => -- up
|
when "0011" => -- up
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0100" => -- sp
|
when "0100" => -- sp
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0101" => -- pc
|
when "0101" => -- pc
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "1000" => -- acca
|
when "1000" => -- acca
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "1001" => -- accb
|
when "1001" => -- accb
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "1010" => -- cc
|
when "1010" => -- cc
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
dp_ctrl <= latch_dp;
|
|
when "1011" => --dp
|
when "1011" => --dp
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= load_dp;
|
dp_ctrl <= load_dp;
|
when others =>
|
when others =>
|
ix_ctrl <= latch_ix;
|
null;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
end case;
|
end case;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
--
|
st_ctrl <= pull_st;
|
st_ctrl <= pull_st;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
next_state <= saved_state;
|
|
|
when exg_state =>
|
when exg_state =>
|
-- default
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
md_ctrl <= latch_md;
|
|
-- save destination register
|
-- save destination register
|
case md(3 downto 0) is
|
case md(3 downto 0) is
|
when "0000" =>
|
when "0000" =>
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
when "0001" =>
|
when "0001" =>
|
| Line 6202... |
Line 3997... |
left_ctrl <= md_left;
|
left_ctrl <= md_left;
|
end case;
|
end case;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_tfr;
|
alu_ctrl <= alu_tfr;
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
-- call tranfer microcode
|
-- call tranfer microcode
|
st_ctrl <= push_st;
|
st_ctrl <= push_st;
|
return_state <= exg1_state;
|
return_state <= exg1_state;
|
next_state <= tfr_state;
|
next_state <= tfr_state;
|
|
|
when exg1_state =>
|
when exg1_state =>
|
-- default
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= latch_md;
|
|
-- restore destination
|
-- restore destination
|
left_ctrl <= ea_left;
|
left_ctrl <= ea_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_tfr;
|
alu_ctrl <= alu_tfr;
|
-- save as source register
|
-- save as source register
|
case md(7 downto 4) is
|
case md(7 downto 4) is
|
when "0000" => -- accd
|
when "0000" => -- accd
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0001" => -- ix
|
when "0001" => -- ix
|
ix_ctrl <= load_ix;
|
ix_ctrl <= load_ix;
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0010" => -- iy
|
when "0010" => -- iy
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= load_iy;
|
iy_ctrl <= load_iy;
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0011" => -- up
|
when "0011" => -- up
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0100" => -- sp
|
when "0100" => -- sp
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "0101" => -- pc
|
when "0101" => -- pc
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= load_pc;
|
pc_ctrl <= load_pc;
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "1000" => -- acca
|
when "1000" => -- acca
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= load_acca;
|
acca_ctrl <= load_acca;
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "1001" => -- accb
|
when "1001" => -- accb
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
when "1010" => -- cc
|
when "1010" => -- cc
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
dp_ctrl <= latch_dp;
|
|
when "1011" => --dp
|
when "1011" => --dp
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= load_dp;
|
dp_ctrl <= load_dp;
|
when others =>
|
when others =>
|
acca_ctrl <= latch_acca;
|
null;
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
cc_ctrl <= latch_cc;
|
|
dp_ctrl <= latch_dp;
|
|
end case;
|
end case;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
when mul_state =>
|
when mul_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- move acca to md
|
-- move acca to md
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= latch_cc;
|
|
md_ctrl <= load_md;
|
md_ctrl <= load_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mulea_state;
|
next_state <= mulea_state;
|
|
|
when mulea_state =>
|
when mulea_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
md_ctrl <= latch_md;
|
|
-- move accb to ea
|
-- move accb to ea
|
left_ctrl <= accb_left;
|
left_ctrl <= accb_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_st16;
|
alu_ctrl <= alu_st16;
|
cc_ctrl <= latch_cc;
|
|
ea_ctrl <= load_ea;
|
ea_ctrl <= load_ea;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= muld_state;
|
next_state <= muld_state;
|
|
|
when muld_state =>
|
when muld_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
md_ctrl <= latch_md;
|
|
-- clear accd
|
-- clear accd
|
left_ctrl <= acca_left;
|
left_ctrl <= acca_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= zero_right;
|
alu_ctrl <= alu_ld8;
|
alu_ctrl <= alu_ld8;
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul0_state;
|
next_state <= mul0_state;
|
|
|
when mul0_state =>
|
when mul0_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 0 of ea set, add accd to md
|
-- if bit 0 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6471... |
Line 4073... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul1_state;
|
next_state <= mul1_state;
|
|
|
when mul1_state =>
|
when mul1_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 1 of ea set, add accd to md
|
-- if bit 1 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6504... |
Line 4088... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul2_state;
|
next_state <= mul2_state;
|
|
|
when mul2_state =>
|
when mul2_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 2 of ea set, add accd to md
|
-- if bit 2 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6537... |
Line 4103... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul3_state;
|
next_state <= mul3_state;
|
|
|
when mul3_state =>
|
when mul3_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 3 of ea set, add accd to md
|
-- if bit 3 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6570... |
Line 4118... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul4_state;
|
next_state <= mul4_state;
|
|
|
when mul4_state =>
|
when mul4_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
nmi_ctrl <= latch_nmi;
|
|
pre_ctrl <= latch_pre;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 4 of ea set, add accd to md
|
-- if bit 4 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6603... |
Line 4133... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul5_state;
|
next_state <= mul5_state;
|
|
|
when mul5_state =>
|
when mul5_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 5 of ea set, add accd to md
|
-- if bit 5 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6636... |
Line 4148... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul6_state;
|
next_state <= mul6_state;
|
|
|
when mul6_state =>
|
when mul6_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 6 of ea set, add accd to md
|
-- if bit 6 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6669... |
Line 4163... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= mul7_state;
|
next_state <= mul7_state;
|
|
|
when mul7_state =>
|
when mul7_state =>
|
-- default
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- if bit 7 of ea set, add accd to md
|
-- if bit 7 of ea set, add accd to md
|
left_ctrl <= accd_left;
|
left_ctrl <= accd_left;
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
right_ctrl <= md_right;
|
right_ctrl <= md_right;
|
else
|
else
|
| Line 6702... |
Line 4178... |
alu_ctrl <= alu_mul;
|
alu_ctrl <= alu_mul;
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
acca_ctrl <= load_hi_acca;
|
acca_ctrl <= load_hi_acca;
|
accb_ctrl <= load_accb;
|
accb_ctrl <= load_accb;
|
md_ctrl <= shiftl_md;
|
md_ctrl <= shiftl_md;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- Enter here on pushs
|
-- Enter here on pushs
|
-- ea holds post byte
|
-- ea holds post byte
|
--
|
--
|
when pshs_state =>
|
when pshs_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp if any registers to be pushed
|
-- decrement sp if any registers to be pushed
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(7 downto 0) = "00000000" then
|
if ea(7 downto 0) = "00000000" then
|
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
else
|
else
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= pshs_pcl_state;
|
next_state <= pshs_pcl_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pshs_upl_state;
|
next_state <= pshs_upl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
| Line 6767... |
Line 4215... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_pcl_state =>
|
when pshs_pcl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshs_pch_state;
|
next_state <= pshs_pch_state;
|
|
|
when pshs_pch_state =>
|
when pshs_pch_state =>
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(6 downto 0) = "0000000" then
|
if ea(6 downto 0) = "0000000" then
|
| Line 6824... |
Line 4238... |
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= pshs_upl_state;
|
next_state <= pshs_upl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pshs_iyl_state;
|
next_state <= pshs_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
| Line 6847... |
Line 4258... |
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
|
|
when pshs_upl_state =>
|
when pshs_upl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_lo_dout;
|
dout_ctrl <= up_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshs_uph_state;
|
next_state <= pshs_uph_state;
|
|
|
when pshs_uph_state =>
|
when pshs_uph_state =>
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(5 downto 0) = "000000" then
|
if ea(5 downto 0) = "000000" then
|
| Line 6902... |
Line 4281... |
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_hi_dout;
|
dout_ctrl <= up_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= pshs_iyl_state;
|
next_state <= pshs_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshs_ixl_state;
|
next_state <= pshs_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
| Line 6922... |
Line 4298... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_iyl_state =>
|
when pshs_iyl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write iy low
|
-- write iy low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_lo_dout;
|
dout_ctrl <= iy_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshs_iyh_state;
|
next_state <= pshs_iyh_state;
|
|
|
when pshs_iyh_state =>
|
when pshs_iyh_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(4 downto 0) = "00000" then
|
if ea(4 downto 0) = "00000" then
|
| Line 6978... |
Line 4321... |
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write iy hi
|
-- write iy hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_hi_dout;
|
dout_ctrl <= iy_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= pshs_ixl_state;
|
next_state <= pshs_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshs_dp_state;
|
next_state <= pshs_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_ixl_state =>
|
when pshs_ixl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshs_ixh_state;
|
next_state <= pshs_ixh_state;
|
|
|
when pshs_ixh_state =>
|
when pshs_ixh_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(3 downto 0) = "0000" then
|
if ea(3 downto 0) = "0000" then
|
| Line 7052... |
Line 4359... |
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_hi_dout;
|
dout_ctrl <= ix_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= pshs_dp_state;
|
next_state <= pshs_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
| Line 7068... |
Line 4372... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_dp_state =>
|
when pshs_dp_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(2 downto 0) = "000" then
|
if ea(2 downto 0) = "000" then
|
| Line 7095... |
Line 4384... |
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write dp
|
-- write dp
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= dp_dout;
|
dout_ctrl <= dp_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= pshs_accb_state;
|
next_state <= pshs_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
| Line 7109... |
Line 4395... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_accb_state =>
|
when pshs_accb_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(1 downto 0) = "00" then
|
if ea(1 downto 0) = "00" then
|
| Line 7136... |
Line 4407... |
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
end if;
|
end if;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= pshs_acca_state;
|
next_state <= pshs_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_acca_state =>
|
when pshs_acca_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
| Line 7175... |
Line 4428... |
sp_ctrl <= latch_sp;
|
sp_ctrl <= latch_sp;
|
end if;
|
end if;
|
-- write acca
|
-- write acca
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= pshs_cc_state;
|
next_state <= pshs_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshs_cc_state =>
|
when pshs_cc_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle sp
|
-- idle sp
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_nop;
|
|
sp_ctrl <= latch_sp;
|
|
-- write cc
|
-- write cc
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= cc_dout;
|
dout_ctrl <= cc_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- enter here on PULS
|
-- enter here on PULS
|
-- ea hold register mask
|
-- ea hold register mask
|
--
|
--
|
when puls_state =>
|
when puls_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle SP
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
sp_ctrl <= latch_sp;
|
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= puls_cc_state;
|
next_state <= puls_cc_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= puls_acca_state;
|
next_state <= puls_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
| Line 7265... |
Line 4467... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_cc_state =>
|
when puls_cc_state =>
|
-- default registers
|
-- increment sp
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- Increment SP
|
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read cc
|
-- read cc
|
cc_ctrl <= pull_cc;
|
cc_ctrl <= pull_cc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= cc_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= puls_acca_state;
|
next_state <= puls_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= puls_accb_state;
|
next_state <= puls_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
| Line 7310... |
Line 4494... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_acca_state =>
|
when puls_acca_state =>
|
-- default registers
|
-- increment sp
|
cc_ctrl <= latch_cc;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- Increment SP
|
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read acca
|
-- read acca
|
acca_ctrl <= pull_acca;
|
acca_ctrl <= pull_acca;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= acca_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= puls_accb_state;
|
next_state <= puls_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= puls_dp_state;
|
next_state <= puls_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
| Line 7353... |
Line 4519... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_accb_state =>
|
when puls_accb_state =>
|
-- default
|
-- increment sp
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- Increment SP
|
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read accb
|
-- read accb
|
accb_ctrl <= pull_accb;
|
accb_ctrl <= pull_accb;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= accb_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= puls_dp_state;
|
next_state <= puls_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= puls_ixh_state;
|
next_state <= puls_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
| Line 7394... |
Line 4542... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_dp_state =>
|
when puls_dp_state =>
|
-- default
|
-- increment sp
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle sp
|
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read dp
|
-- read dp
|
dp_ctrl <= pull_dp;
|
dp_ctrl <= pull_dp;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= dp_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= puls_ixh_state;
|
next_state <= puls_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
| Line 7433... |
Line 4563... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_ixh_state =>
|
when puls_ixh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull ix hi
|
-- pull ix hi
|
ix_ctrl <= pull_hi_ix;
|
ix_ctrl <= pull_hi_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= ix_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= puls_ixl_state;
|
next_state <= puls_ixl_state;
|
|
|
when puls_ixl_state =>
|
when puls_ixl_state =>
|
-- default
|
-- increment sp
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle sp
|
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read ix low
|
-- read ix low
|
ix_ctrl <= pull_lo_ix;
|
ix_ctrl <= pull_lo_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= ix_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= puls_iyh_state;
|
next_state <= puls_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_iyh_state =>
|
when puls_iyh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull iy hi
|
-- pull iy hi
|
iy_ctrl <= pull_hi_iy;
|
iy_ctrl <= pull_hi_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= iy_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= puls_iyl_state;
|
next_state <= puls_iyl_state;
|
|
|
when puls_iyl_state =>
|
when puls_iyl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read iy low
|
-- read iy low
|
iy_ctrl <= pull_lo_iy;
|
iy_ctrl <= pull_lo_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= iy_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= puls_uph_state;
|
next_state <= puls_uph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_uph_state =>
|
when puls_uph_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull up hi
|
-- pull up hi
|
up_ctrl <= pull_hi_up;
|
up_ctrl <= pull_hi_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= up_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= puls_upl_state;
|
next_state <= puls_upl_state;
|
|
|
when puls_upl_state =>
|
when puls_upl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read up low
|
-- read up low
|
up_ctrl <= pull_lo_up;
|
up_ctrl <= pull_lo_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= up_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= puls_pch_state;
|
next_state <= puls_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when puls_pch_state =>
|
when puls_pch_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull pc hi
|
-- pull pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= pc_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= puls_pcl_state;
|
next_state <= puls_pcl_state;
|
|
|
when puls_pcl_state =>
|
when puls_pcl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read pc low
|
-- read pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= pc_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- Enter here on pshu
|
-- Enter here on pshu
|
-- ea holds post byte
|
-- ea holds post byte
|
--
|
--
|
when pshu_state =>
|
when pshu_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
dp_ctrl <= latch_dp;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement up if any registers to be pushed
|
-- decrement up if any registers to be pushed
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(7 downto 0) = "00000000" then
|
if ea(7 downto 0) = "00000000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write idle bus
|
-- write idle bus
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= pshu_pcl_state;
|
next_state <= pshu_pcl_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pshu_spl_state;
|
next_state <= pshu_spl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
| Line 7741... |
Line 4706... |
end if;
|
end if;
|
--
|
--
|
-- push PC onto U stack
|
-- push PC onto U stack
|
--
|
--
|
when pshu_pcl_state =>
|
when pshu_pcl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshu_pch_state;
|
next_state <= pshu_pch_state;
|
|
|
when pshu_pch_state =>
|
when pshu_pch_state =>
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(6 downto 0) = "0000000" then
|
if ea(6 downto 0) = "0000000" then
|
| Line 7796... |
Line 4729... |
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= pshu_spl_state;
|
next_state <= pshu_spl_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pshu_iyl_state;
|
next_state <= pshu_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
| Line 7818... |
Line 4748... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_spl_state =>
|
when pshu_spl_state =>
|
-- default
|
-- decrement up
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write pc low
|
-- write sp low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= sp_lo_dout;
|
dout_ctrl <= sp_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshu_sph_state;
|
next_state <= pshu_sph_state;
|
|
|
when pshu_sph_state =>
|
when pshu_sph_state =>
|
cc_ctrl <= latch_cc;
|
-- decrement up
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(5 downto 0) = "000000" then
|
if ea(5 downto 0) = "000000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
| Line 7873... |
Line 4771... |
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write sp hi
|
-- write sp hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= sp_hi_dout;
|
dout_ctrl <= sp_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= pshu_iyl_state;
|
next_state <= pshu_iyl_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pshu_ixl_state;
|
next_state <= pshu_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
| Line 7893... |
Line 4788... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_iyl_state =>
|
when pshu_iyl_state =>
|
-- default
|
-- decrement up
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write iy low
|
-- write iy low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= iy_lo_dout;
|
dout_ctrl <= iy_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshu_iyh_state;
|
next_state <= pshu_iyh_state;
|
|
|
when pshu_iyh_state =>
|
when pshu_iyh_state =>
|
-- default registers
|
-- decrement up
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(4 downto 0) = "00000" then
|
if ea(4 downto 0) = "00000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
| Line 7949... |
Line 4811... |
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write iy hi
|
-- write iy hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= iy_hi_dout;
|
dout_ctrl <= iy_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= pshu_ixl_state;
|
next_state <= pshu_ixl_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pshu_dp_state;
|
next_state <= pshu_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_ixl_state =>
|
when pshu_ixl_state =>
|
-- default
|
-- decrement up
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pshu_ixh_state;
|
next_state <= pshu_ixh_state;
|
|
|
when pshu_ixh_state =>
|
when pshu_ixh_state =>
|
-- default registers
|
-- decrement up
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(3 downto 0) = "0000" then
|
if ea(3 downto 0) = "0000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
| Line 8023... |
Line 4849... |
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= ix_hi_dout;
|
dout_ctrl <= ix_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= pshu_dp_state;
|
next_state <= pshu_dp_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
| Line 8039... |
Line 4862... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_dp_state =>
|
when pshu_dp_state =>
|
-- default registers
|
-- decrement up
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(2 downto 0) = "000" then
|
if ea(2 downto 0) = "000" then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
else
|
else
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write accb
|
-- write dp
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= dp_dout;
|
dout_ctrl <= dp_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= pshu_accb_state;
|
next_state <= pshu_accb_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
| Line 8080... |
Line 4885... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_accb_state =>
|
when pshu_accb_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement up
|
-- decrement up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(1 downto 0) = "00" then
|
if ea(1 downto 0) = "00" then
|
| Line 8107... |
Line 4897... |
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= pshu_acca_state;
|
next_state <= pshu_acca_state;
|
elsif ea(0) = '1' then
|
elsif ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_acca_state =>
|
when pshu_acca_state =>
|
-- default registers
|
-- decrement up
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
if ea(0) = '0' then
|
if ea(0) = '0' then
|
up_ctrl <= latch_up;
|
up_ctrl <= latch_up;
|
| Line 8146... |
Line 4918... |
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
end if;
|
end if;
|
-- write acca
|
-- write acca
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= pshu_cc_state;
|
next_state <= pshu_cc_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pshu_cc_state =>
|
when pshu_cc_state =>
|
-- default registers
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle up
|
-- idle up
|
left_ctrl <= up_left;
|
|
right_ctrl <= one_right;
|
|
cc_ctrl <= latch_cc;
|
|
alu_ctrl <= alu_nop;
|
|
up_ctrl <= latch_up;
|
|
-- write cc
|
-- write cc
|
addr_ctrl <= pushu_ad;
|
addr_ctrl <= pushu_ad;
|
dout_ctrl <= cc_dout;
|
dout_ctrl <= cc_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- enter here on PULU
|
-- enter here on PULU
|
-- ea hold register mask
|
-- ea hold register mask
|
--
|
--
|
when pulu_state =>
|
when pulu_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle UP
|
-- idle UP
|
left_ctrl <= up_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_add16;
|
|
up_ctrl <= latch_up;
|
|
-- idle bus
|
-- idle bus
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(0) = '1' then
|
if ea(0) = '1' then
|
next_state <= pulu_cc_state;
|
next_state <= pulu_cc_state;
|
elsif ea(1) = '1' then
|
elsif ea(1) = '1' then
|
next_state <= pulu_acca_state;
|
next_state <= pulu_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
| Line 8236... |
Line 4959... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_cc_state =>
|
when pulu_cc_state =>
|
-- default registers
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read cc
|
-- read cc
|
cc_ctrl <= pull_cc;
|
cc_ctrl <= pull_cc;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= cc_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(1) = '1' then
|
if ea(1) = '1' then
|
next_state <= pulu_acca_state;
|
next_state <= pulu_acca_state;
|
elsif ea(2) = '1' then
|
elsif ea(2) = '1' then
|
next_state <= pulu_accb_state;
|
next_state <= pulu_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
| Line 8281... |
Line 4986... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_acca_state =>
|
when pulu_acca_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read acca
|
-- read acca
|
acca_ctrl <= pull_acca;
|
acca_ctrl <= pull_acca;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= acca_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(2) = '1' then
|
if ea(2) = '1' then
|
next_state <= pulu_accb_state;
|
next_state <= pulu_accb_state;
|
elsif ea(3) = '1' then
|
elsif ea(3) = '1' then
|
next_state <= pulu_dp_state;
|
next_state <= pulu_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
| Line 8324... |
Line 5011... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_accb_state =>
|
when pulu_accb_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read accb
|
-- read accb
|
accb_ctrl <= pull_accb;
|
accb_ctrl <= pull_accb;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= accb_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(3) = '1' then
|
if ea(3) = '1' then
|
next_state <= pulu_dp_state;
|
next_state <= pulu_dp_state;
|
elsif ea(4) = '1' then
|
elsif ea(4) = '1' then
|
next_state <= pulu_ixh_state;
|
next_state <= pulu_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
| Line 8365... |
Line 5034... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_dp_state =>
|
when pulu_dp_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read dp
|
-- read dp
|
dp_ctrl <= pull_dp;
|
dp_ctrl <= pull_dp;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= dp_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(4) = '1' then
|
if ea(4) = '1' then
|
next_state <= pulu_ixh_state;
|
next_state <= pulu_ixh_state;
|
elsif ea(5) = '1' then
|
elsif ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
| Line 8404... |
Line 5055... |
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_ixh_state =>
|
when pulu_ixh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- pull ix hi
|
-- read ix hi
|
ix_ctrl <= pull_hi_ix;
|
ix_ctrl <= pull_hi_ix;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= ix_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pulu_ixl_state;
|
next_state <= pulu_ixl_state;
|
|
|
when pulu_ixl_state =>
|
when pulu_ixl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read ix low
|
-- read ix low
|
ix_ctrl <= pull_lo_ix;
|
ix_ctrl <= pull_lo_ix;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= ix_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(5) = '1' then
|
if ea(5) = '1' then
|
next_state <= pulu_iyh_state;
|
next_state <= pulu_iyh_state;
|
elsif ea(6) = '1' then
|
elsif ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_iyh_state =>
|
when pulu_iyh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- pull iy hi
|
-- read iy hi
|
iy_ctrl <= pull_hi_iy;
|
iy_ctrl <= pull_hi_iy;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= iy_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pulu_iyl_state;
|
next_state <= pulu_iyl_state;
|
|
|
when pulu_iyl_state =>
|
when pulu_iyl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read iy low
|
-- read iy low
|
iy_ctrl <= pull_lo_iy;
|
iy_ctrl <= pull_lo_iy;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= iy_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(6) = '1' then
|
if ea(6) = '1' then
|
next_state <= pulu_sph_state;
|
next_state <= pulu_sph_state;
|
elsif ea(7) = '1' then
|
elsif ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_sph_state =>
|
when pulu_sph_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- pull sp hi
|
-- read sp hi
|
sp_ctrl <= pull_hi_sp;
|
sp_ctrl <= pull_hi_sp;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= up_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pulu_spl_state;
|
next_state <= pulu_spl_state;
|
|
|
when pulu_spl_state =>
|
when pulu_spl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read sp low
|
-- read sp low
|
sp_ctrl <= pull_lo_sp;
|
sp_ctrl <= pull_lo_sp;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= up_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if ea(7) = '1' then
|
if ea(7) = '1' then
|
next_state <= pulu_pch_state;
|
next_state <= pulu_pch_state;
|
else
|
else
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
|
|
when pulu_pch_state =>
|
when pulu_pch_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- pull pc hi
|
-- pull pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= pc_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= pulu_pcl_state;
|
next_state <= pulu_pcl_state;
|
|
|
when pulu_pcl_state =>
|
when pulu_pcl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
sp_ctrl <= latch_sp;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment up
|
-- increment up
|
left_ctrl <= up_left;
|
left_ctrl <= up_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
up_ctrl <= load_up;
|
up_ctrl <= load_up;
|
-- read pc low
|
-- read pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pullu_ad;
|
addr_ctrl <= pullu_ad;
|
dout_ctrl <= pc_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- pop the Condition codes
|
-- pop the Condition codes
|
--
|
--
|
when rti_cc_state =>
|
when rti_cc_state =>
|
-- default registers
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read cc
|
-- read cc
|
cc_ctrl <= pull_cc;
|
cc_ctrl <= pull_cc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= cc_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_entire_state;
|
next_state <= rti_entire_state;
|
|
|
--
|
--
|
-- Added RTI cycle 11th July 2006 John Kent.
|
-- Added RTI cycle 11th July 2006 John Kent.
|
-- test the "Entire" Flag
|
-- test the "Entire" Flag
|
-- that has just been popped off the stack
|
-- that has just been popped off the stack
|
--
|
--
|
when rti_entire_state =>
|
when rti_entire_state =>
|
-- default registers
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle sp
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_nop;
|
|
sp_ctrl <= latch_sp;
|
|
-- idle cc
|
|
cc_ctrl <= latch_cc;
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= cc_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
--
|
--
|
-- The Entire flag must be recovered from the stack
|
-- The Entire flag must be recovered from the stack
|
-- before testing.
|
-- before testing.
|
--
|
--
|
if cc(EBIT) = '1' then
|
if cc(EBIT) = '1' then
|
| Line 8728... |
Line 5191... |
else
|
else
|
next_state <= rti_pch_state;
|
next_state <= rti_pch_state;
|
end if;
|
end if;
|
|
|
when rti_acca_state =>
|
when rti_acca_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read acca
|
-- read acca
|
acca_ctrl <= pull_acca;
|
acca_ctrl <= pull_acca;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= acca_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_accb_state;
|
next_state <= rti_accb_state;
|
|
|
when rti_accb_state =>
|
when rti_accb_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read accb
|
-- read accb
|
accb_ctrl <= pull_accb;
|
accb_ctrl <= pull_accb;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= accb_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_dp_state;
|
next_state <= rti_dp_state;
|
|
|
when rti_dp_state =>
|
when rti_dp_state =>
|
-- default registers
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read dp
|
-- read dp
|
dp_ctrl <= pull_dp;
|
dp_ctrl <= pull_dp;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= dp_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_ixh_state;
|
next_state <= rti_ixh_state;
|
|
|
when rti_ixh_state =>
|
when rti_ixh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read ix hi
|
-- read ix hi
|
ix_ctrl <= pull_hi_ix;
|
ix_ctrl <= pull_hi_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= ix_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_ixl_state;
|
next_state <= rti_ixl_state;
|
|
|
when rti_ixl_state =>
|
when rti_ixl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read ix low
|
-- read ix low
|
ix_ctrl <= pull_lo_ix;
|
ix_ctrl <= pull_lo_ix;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= ix_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_iyh_state;
|
next_state <= rti_iyh_state;
|
|
|
when rti_iyh_state =>
|
when rti_iyh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read iy hi
|
-- read iy hi
|
iy_ctrl <= pull_hi_iy;
|
iy_ctrl <= pull_hi_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= iy_hi_dout;
|
next_state <= rti_iyl_state;
|
--
|
|
st_ctrl <= idle_st;
|
when rti_iyl_state =>
|
return_state <= fetch_state;
|
|
next_state <= rti_iyl_state;
|
|
|
|
when rti_iyl_state =>
|
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read iy low
|
-- read iy low
|
iy_ctrl <= pull_lo_iy;
|
iy_ctrl <= pull_lo_iy;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= iy_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_uph_state;
|
next_state <= rti_uph_state;
|
|
|
|
|
when rti_uph_state =>
|
when rti_uph_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read up hi
|
-- read up hi
|
up_ctrl <= pull_hi_up;
|
up_ctrl <= pull_hi_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= up_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_upl_state;
|
next_state <= rti_upl_state;
|
|
|
when rti_upl_state =>
|
when rti_upl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
iy_ctrl <= latch_iy;
|
|
ix_ctrl <= latch_ix;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- read up low
|
-- read up low
|
up_ctrl <= pull_lo_up;
|
up_ctrl <= pull_lo_up;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= up_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_pch_state;
|
next_state <= rti_pch_state;
|
|
|
when rti_pch_state =>
|
when rti_pch_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull pc hi
|
-- pull pc hi
|
pc_ctrl <= pull_hi_pc;
|
pc_ctrl <= pull_hi_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= pc_hi_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= rti_pcl_state;
|
next_state <= rti_pcl_state;
|
|
|
when rti_pcl_state =>
|
when rti_pcl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- increment sp
|
-- increment sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_add16;
|
alu_ctrl <= alu_add16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- pull pc low
|
-- pull pc low
|
pc_ctrl <= pull_lo_pc;
|
pc_ctrl <= pull_lo_pc;
|
addr_ctrl <= pulls_ad;
|
addr_ctrl <= pulls_ad;
|
dout_ctrl <= pc_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
|
|
--
|
--
|
-- here on IRQ, NMI or FIRQ interrupt
|
-- here on IRQ or NMI interrupt
|
-- pre decrement the sp
|
-- pre decrement the sp
|
|
-- Idle bus cycle
|
--
|
--
|
when int_decr_state =>
|
when int_nmiirq_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= pc_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_entire_state;
|
next_state <= int_entire_state;
|
|
|
--
|
--
|
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
|
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
|
-- clear Entire Flag on FIRQ
|
-- clear Entire Flag on FIRQ
|
-- before stacking all registers
|
-- before stacking all registers
|
--
|
--
|
when int_entire_state =>
|
when int_entire_state =>
|
-- default
|
-- set entire flag
|
acca_ctrl <= latch_acca;
|
alu_ctrl <= alu_see;
|
accb_ctrl <= latch_accb;
|
cc_ctrl <= load_cc;
|
dp_ctrl <= latch_dp;
|
next_state <= int_pcl_state;
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
--
|
up_ctrl <= latch_up;
|
-- here on FIRQ interrupt
|
sp_ctrl <= latch_sp;
|
-- pre decrement the sp
|
pc_ctrl <= latch_pc;
|
-- Idle bus cycle
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
--
|
|
when int_firq_state =>
|
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= zero_right;
|
right_ctrl <= one_right;
|
if iv = FIRQ_VEC then
|
alu_ctrl <= alu_sub16;
|
|
sp_ctrl <= load_sp;
|
|
next_state <= int_fast_state;
|
|
--
|
|
-- clear Entire Flag on FIRQ
|
|
-- before stacking all registers
|
|
--
|
|
when int_fast_state =>
|
-- clear entire flag
|
-- clear entire flag
|
alu_ctrl <= alu_cle;
|
alu_ctrl <= alu_cle;
|
else
|
|
-- set entire flag
|
|
alu_ctrl <= alu_see;
|
|
end if;
|
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= pc_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_pcl_state;
|
next_state <= int_pcl_state;
|
|
|
when int_pcl_state =>
|
when int_pcl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc low
|
-- write pc low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_lo_dout;
|
dout_ctrl <= pc_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_pch_state;
|
next_state <= int_pch_state;
|
|
|
when int_pch_state =>
|
when int_pch_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write pc hi
|
-- write pc hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= pc_hi_dout;
|
dout_ctrl <= pc_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
if cc(EBIT) = '1' then
|
if cc(EBIT) = '1' then
|
next_state <= int_upl_state;
|
next_state <= int_upl_state;
|
else
|
else
|
next_state <= int_cc_state;
|
next_state <= int_cc_state;
|
end if;
|
end if;
|
|
|
when int_upl_state =>
|
when int_upl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write up low
|
-- write up low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_lo_dout;
|
dout_ctrl <= up_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_uph_state;
|
next_state <= int_uph_state;
|
|
|
when int_uph_state =>
|
when int_uph_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= up_hi_dout;
|
dout_ctrl <= up_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_iyl_state;
|
next_state <= int_iyl_state;
|
|
|
when int_iyl_state =>
|
when int_iyl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_lo_dout;
|
dout_ctrl <= iy_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_iyh_state;
|
next_state <= int_iyh_state;
|
|
|
when int_iyh_state =>
|
when int_iyh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= iy_hi_dout;
|
dout_ctrl <= iy_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_ixl_state;
|
next_state <= int_ixl_state;
|
|
|
when int_ixl_state =>
|
when int_ixl_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix low
|
-- write ix low
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_lo_dout;
|
dout_ctrl <= ix_lo_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_ixh_state;
|
next_state <= int_ixh_state;
|
|
|
when int_ixh_state =>
|
when int_ixh_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write ix hi
|
-- write ix hi
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= ix_hi_dout;
|
dout_ctrl <= ix_hi_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_dp_state;
|
next_state <= int_dp_state;
|
|
|
when int_dp_state =>
|
when int_dp_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= dp_dout;
|
dout_ctrl <= dp_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_accb_state;
|
next_state <= int_accb_state;
|
|
|
when int_accb_state =>
|
when int_accb_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write accb
|
-- write accb
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= accb_dout;
|
dout_ctrl <= accb_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_acca_state;
|
next_state <= int_acca_state;
|
|
|
when int_acca_state =>
|
when int_acca_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- decrement sp
|
-- decrement sp
|
left_ctrl <= sp_left;
|
left_ctrl <= sp_left;
|
right_ctrl <= one_right;
|
right_ctrl <= one_right;
|
alu_ctrl <= alu_sub16;
|
alu_ctrl <= alu_sub16;
|
sp_ctrl <= load_sp;
|
sp_ctrl <= load_sp;
|
-- write acca
|
-- write acca
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= acca_dout;
|
dout_ctrl <= acca_dout;
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= int_cc_state;
|
next_state <= int_cc_state;
|
|
|
when int_cc_state =>
|
when int_cc_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
iv_ctrl <= latch_iv;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle sp
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
sp_ctrl <= latch_sp;
|
|
-- write cc
|
-- write cc
|
addr_ctrl <= pushs_ad;
|
addr_ctrl <= pushs_ad;
|
dout_ctrl <= cc_dout;
|
dout_ctrl <= cc_dout;
|
nmi_ctrl <= latch_nmi;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
case iv is
|
case iv is
|
when NMI_VEC =>
|
when NMI_VEC =>
|
next_state <= int_mask_state;
|
next_state <= int_maskif_state;
|
when SWI_VEC =>
|
when SWI_VEC =>
|
next_state <= int_mask_state;
|
next_state <= int_maskif_state;
|
|
when FIRQ_VEC =>
|
|
next_state <= int_maskif_state;
|
when IRQ_VEC =>
|
when IRQ_VEC =>
|
next_state <= int_mask_state;
|
next_state <= int_maski_state;
|
when SWI2_VEC =>
|
when SWI2_VEC =>
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
when FIRQ_VEC =>
|
|
next_state <= int_mask_state;
|
|
when SWI3_VEC =>
|
when SWI3_VEC =>
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
when others =>
|
when others =>
|
if op_code = "00111100" then -- CWAI
|
if op_code = "00111100" then -- CWAI
|
next_state <= int_cwai_state;
|
next_state <= int_cwai_state;
|
| Line 9497... |
Line 5512... |
|
|
--
|
--
|
-- wait here for an inteerupt
|
-- wait here for an inteerupt
|
--
|
--
|
when int_cwai_state =>
|
when int_cwai_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_nop;
|
|
cc_ctrl <= latch_cc;
|
|
sp_ctrl <= latch_sp;
|
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= cc_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
--
|
|
if (nmi_req = '1') and (nmi_ack='0') then
|
if (nmi_req = '1') and (nmi_ack='0') then
|
iv_ctrl <= nmi_iv;
|
iv_ctrl <= nmi_iv;
|
nmi_ctrl <= set_nmi;
|
nmi_ctrl <= set_nmi;
|
next_state <= vect_hi_state;
|
next_state <= int_maskif_state;
|
else
|
else
|
--
|
--
|
-- nmi request is not cleared until nmi input goes low
|
-- nmi request is not cleared until nmi input goes low
|
--
|
--
|
if (nmi_req = '0') and (nmi_ack='1') then
|
if (nmi_req = '0') and (nmi_ack='1') then
|
nmi_ctrl <= reset_nmi;
|
nmi_ctrl <= reset_nmi;
|
else
|
|
nmi_ctrl <= latch_nmi;
|
|
end if;
|
end if;
|
--
|
--
|
-- IRQ is level sensitive
|
|
--
|
|
if (irq = '1') and (cc(IBIT) = '0') then
|
|
iv_ctrl <= irq_iv;
|
|
next_state <= int_mask_state;
|
|
elsif (firq = '1') and (cc(FBIT) = '0') then
|
|
--
|
|
-- FIRQ is level sensitive
|
-- FIRQ is level sensitive
|
--
|
--
|
|
if (firq = '1') and (cc(FBIT) = '0') then
|
iv_ctrl <= firq_iv;
|
iv_ctrl <= firq_iv;
|
next_state <= int_mask_state;
|
next_state <= int_maskif_state;
|
|
--
|
|
-- IRQ is level sensitive
|
|
--
|
|
elsif (irq = '1') and (cc(IBIT) = '0') then
|
|
iv_ctrl <= irq_iv;
|
|
next_state <= int_maski_state;
|
else
|
else
|
iv_ctrl <= latch_iv;
|
iv_ctrl <= reset_iv;
|
next_state <= int_cwai_state;
|
next_state <= int_cwai_state;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when int_mask_state =>
|
when int_maski_state =>
|
-- default
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- Mask IRQ and FIRQ
|
|
left_ctrl <= sp_left;
|
|
right_ctrl <= zero_right;
|
|
--
|
|
-- FIRQ can interrupt an IRQ service routine
|
|
--
|
|
if iv = IRQ_VEC then
|
|
alu_ctrl <= alu_sei;
|
alu_ctrl <= alu_sei;
|
else
|
cc_ctrl <= load_cc;
|
|
next_state <= vect_hi_state;
|
|
|
|
when int_maskif_state =>
|
alu_ctrl <= alu_seif;
|
alu_ctrl <= alu_seif;
|
end if;
|
|
cc_ctrl <= load_cc;
|
cc_ctrl <= load_cc;
|
sp_ctrl <= latch_sp;
|
|
-- idle bus cycle
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= vect_hi_state;
|
next_state <= vect_hi_state;
|
|
|
--
|
--
|
-- According to the 6809 programming manual:
|
-- According to the 6809 programming manual:
|
-- If an interrupt is received and is masked
|
-- If an interrupt is received and is masked
|
| Line 9601... |
Line 5563... |
-- will be generated.
|
-- will be generated.
|
-- Note that I don't wait 3 clock cycles.
|
-- Note that I don't wait 3 clock cycles.
|
-- John Kent 11th July 2006
|
-- John Kent 11th July 2006
|
--
|
--
|
when sync_state =>
|
when sync_state =>
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
ea_ctrl <= latch_ea;
|
|
--
|
|
left_ctrl <= pc_left;
|
|
right_ctrl <= one_right;
|
|
alu_ctrl <= alu_nop;
|
|
-- idle bus
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= cc_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
--
|
|
if (nmi_req = '1') and (nmi_ack='0') then
|
if (nmi_req = '1') and (nmi_ack='0') then
|
iv_ctrl <= nmi_iv;
|
iv_ctrl <= nmi_iv;
|
nmi_ctrl <= set_nmi;
|
nmi_ctrl <= set_nmi;
|
next_state <= int_decr_state;
|
next_state <= int_nmiirq_state;
|
else
|
else
|
--
|
--
|
-- nmi request is not cleared until nmi input goes low
|
-- nmi request is not cleared until nmi input goes low
|
--
|
--
|
if (nmi_req = '0') and (nmi_ack='1') then
|
if (nmi_req = '0') and (nmi_ack='1') then
|
|
iv_ctrl <= reset_iv;
|
nmi_ctrl <= reset_nmi;
|
nmi_ctrl <= reset_nmi;
|
else
|
|
nmi_ctrl <= latch_nmi;
|
|
end if;
|
end if;
|
--
|
--
|
-- IRQ is level sensitive
|
-- FIRQ is level sensitive
|
--
|
--
|
if (irq = '1') then
|
if (firq = '1') then
|
iv_ctrl <= irq_iv;
|
if (cc(FBIT) = '0') then
|
if (cc(IBIT) = '0') then
|
iv_ctrl <= firq_iv;
|
next_state <= int_decr_state;
|
next_state <= int_firq_state;
|
else
|
else
|
|
iv_ctrl <= reset_iv;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
elsif (firq = '1') then
|
|
--
|
--
|
-- FIRQ is level sensitive
|
-- IRQ is level sensitive
|
--
|
--
|
iv_ctrl <= firq_iv;
|
elsif (irq = '1') then
|
if (cc(FBIT) = '0') then
|
if (cc(IBIT) = '0') then
|
next_state <= int_decr_state;
|
iv_ctrl <= irq_iv;
|
|
next_state <= int_nmiirq_state;
|
else
|
else
|
|
iv_ctrl <= reset_iv;
|
next_state <= fetch_state;
|
next_state <= fetch_state;
|
end if;
|
end if;
|
else
|
else
|
iv_ctrl <= latch_iv;
|
iv_ctrl <= reset_iv;
|
next_state <= sync_state;
|
next_state <= sync_state;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
|
when halt_state =>
|
when halt_state =>
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- idle ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
sp_ctrl <= latch_sp;
|
|
-- idle bus cycle
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
if halt = '1' then
|
if halt = '1' then
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= halt_state;
|
next_state <= halt_state;
|
else
|
else
|
st_ctrl <= pull_st;
|
next_state <= fetch_state;
|
return_state <= fetch_state;
|
|
next_state <= saved_state;
|
|
end if;
|
end if;
|
|
|
when others => -- halt on undefine states
|
when others => -- halt on undefine states
|
-- default
|
|
cc_ctrl <= latch_cc;
|
|
acca_ctrl <= latch_acca;
|
|
accb_ctrl <= latch_accb;
|
|
dp_ctrl <= latch_dp;
|
|
ix_ctrl <= latch_ix;
|
|
iy_ctrl <= latch_iy;
|
|
up_ctrl <= latch_up;
|
|
sp_ctrl <= latch_sp;
|
|
pc_ctrl <= latch_pc;
|
|
md_ctrl <= latch_md;
|
|
iv_ctrl <= latch_iv;
|
|
op_ctrl <= latch_op;
|
|
pre_ctrl <= latch_pre;
|
|
nmi_ctrl <= latch_nmi;
|
|
ea_ctrl <= latch_ea;
|
|
-- do nothing in ALU
|
|
left_ctrl <= acca_left;
|
|
right_ctrl <= zero_right;
|
|
alu_ctrl <= alu_nop;
|
|
-- idle bus cycle
|
|
addr_ctrl <= idle_ad;
|
|
dout_ctrl <= md_lo_dout;
|
|
--
|
|
st_ctrl <= idle_st;
|
|
return_state <= fetch_state;
|
|
next_state <= error_state;
|
next_state <= error_state;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
end rtl;
|
end rtl;
|
