OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [datram.vhd] - Diff between revs 66 and 99

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 66 Rev 99
Line 1... Line 1...
--===========================================================================--
--===========================================================================--
--
--                                                                           --
--  S Y N T H E Z I A B L E    Dynamic Address Translation Registers
--         Synthesizable SWTPc 6809 Dynamic Address Translation Table        --
--
--                                                                           --
--  www.OpenCores.Org - December 2002
--===========================================================================--
--  This core adheres to the GNU public license  
 
--
--
-- File name      : datram.vhd
-- File name      : datram.vhd
--
--
-- entity name    : dat_ram
--  Entity name    : dat_ram
--
--
-- Purpose        : Implements a Dynamic Address Translation RAM module
-- Purpose        : Implements a Dynamic Address Translation RAM module
 
--                   as found in the SWTPc MP-09 CPU card.
--                  Maps the high order 4 address bits to 8 address lines
--                  Maps the high order 4 address bits to 8 address lines
--                  extending the memory addressing range to 1 Mbytes
--                   extending the memory addressing range from 64K to 1MByte
--                  Memory segments are mapped on 4 KByte boundaries
--                  Memory segments are mapped on 4 KByte boundaries
--                  The DAT registers map to the top of memory 
--                   The DAT registers are mapped at the the top of memory 
--                  ($FFF0 - $FFFF) and are write only so can map behind ROM.
--                  ($FFF0 - $FFFF) and are write only so can map behind ROM.
--                  Since the DAT is not supported by SWTBUG for the 6800,
--                  Since the DAT is not supported by SWTBUG for the 6800,
--                  the resgisters reset state map the bottom 64K of RAM. 
--                  the resgisters reset state map the bottom 64K of RAM. 
--                  
--                  
-- Dependencies   : ieee.Std_Logic_1164
--  Dependencies   : ieee.std_logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_unsigned
 
--                   unisim.vcomponents
--
--
-- Author         : John E. Kent      
-- Author         : John E. Kent      
--
--
--===========================================================================----
--  Email          : dilbert57@opencores.org      
--
--
-- Revision History:
--  Web            : http://opencores.org/project,system09
--
--
-- Date          Revision  Author 
--  Description    :
-- 10 Nov 2002   0.1       John Kent
 
--
--
-- 21 Nov 2006   0.2       John Kent
 
-- Inverted bottom 4 bits of dat_addr
 
-- so that it is compatible with SWTPc MP-09 card.
 
-- DAT is initializedas follows:
-- DAT is initializedas follows:
--
--
-- DAT    Dat           Logical Physical
-- DAT    Dat           Logical Physical
-- Reg    Val           Addr    Addr
-- Reg    Val           Addr    Addr
--      fff0 - 0f - page 0 - $0xxx = $00xxx (RAM)
--      fff0 - 0f - page 0 - $0xxx = $00xxx (RAM)
Line 51... Line 48...
--      fffb - 04 - page 0 - $bxxx = $0bxxx (RAM)
--      fffb - 04 - page 0 - $bxxx = $0bxxx (RAM)
--      fffc - 03 - page 0 - $cxxx = $0cxxx (RAM)
--      fffc - 03 - page 0 - $cxxx = $0cxxx (RAM)
--      fffd - 02 - page 0 - $dxxx = $0dxxx (RAM)
--      fffd - 02 - page 0 - $dxxx = $0dxxx (RAM)
--      fffe - f1 - page 0 - $exxx = $fexxx (I/O)
--      fffe - f1 - page 0 - $exxx = $fexxx (I/O)
--      ffff - f0 - page 0 - $fxxx = $ffxxx (ROM/DMFA2)
--      ffff - f0 - page 0 - $fxxx = $ffxxx (ROM/DMFA2)
 
--
-- 25 Feb 2007   0.3      John Kent
--  Copyright (C) 2003 - 2010 John Kent
-- modify the sensitivity lists
--
 
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
 
--
 
--  This program is distributed in the hope that it will be useful,
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
 
--
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--
 
--===========================================================================--
 
--                                                                           --
 
--                              Revision  History                            --
 
--                                                                           --
 
--===========================================================================--
 
--
 
-- Version Date        Author     Changes
 
--
 
-- 0.1     2002-11-10  John Kent  Initial version
 
--
 
-- 0.2     2006-11-21  John Kent  Inverted bottom 4 bits of dat_addr
 
--                                so that it is compatible with SWTPc MP-09 card.
 
--
 
-- 0.3     2007-02-25  John Kent  Modify the sensitivity lists
 
--
 
-- 0.4     2010-06-17  John Kent  Update header and added GPL
--
--
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
Line 67... Line 93...
entity dat_ram is
entity dat_ram is
        port (
        port (
         clk       : in  std_logic;
         clk       : in  std_logic;
    rst       : in  std_logic;
    rst       : in  std_logic;
    cs        : in  std_logic;
    cs        : in  std_logic;
    rw        : in  std_logic;
 
    addr_hi   : in  std_logic_vector(3 downto 0);
    addr_hi   : in  std_logic_vector(3 downto 0);
    addr_lo   : in  std_logic_vector(3 downto 0);
    addr_lo   : in  std_logic_vector(3 downto 0);
 
    rw        : in  std_logic;
    data_in   : in  std_logic_vector(7 downto 0);
    data_in   : in  std_logic_vector(7 downto 0);
         data_out  : out std_logic_vector(7 downto 0));
         data_out  : out std_logic_vector(7 downto 0));
end dat_ram;
end dat_ram;
 
 
architecture rtl of dat_ram is
architecture rtl of dat_ram is

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.