| Line 1... |
Line 1... |
--===========================================================================----
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--===========================================================================--
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--
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-- --
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-- S Y N T H E Z I A B L E spp - Simple Parallel Port
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-- Synthesizable Simple Parallel Port --
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--
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-- --
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-- www.OpenCores.Org - September 2003
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--===========================================================================--
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-- This core adheres to the GNU public license
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--
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--
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-- File name : spp.vhd
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-- File name : spp.vhd
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--
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--
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-- Purpose : Simple Parallel Port for System09
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-- Entity name : spp
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--
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-- Purpose : implements a Simple Parallel Port for System09
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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--
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--
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-- Uses : None
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-- Uses : None
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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--
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--===========================================================================----
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-- Email : dilbert57@opencores.org
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--
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--
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-- Revision History:
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-- Web : http://opencores.org/project,system09
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--===========================================================================--
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--
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--
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-- Version 0.1 - 6th Sep 2008
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-- Description : Register Memory Map
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-- Generated from ioport.vhd
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--
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--
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--===========================================================================
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-- Address MSB LSB
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-- Bit: 7 6 5 4 3 2 1 0
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-- Base+$00 (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
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-- Base+$01 (SPP Status port) Read Pin: ~11 10 12 13 15 - - -
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-- Base+$02 (SPP Control port) Write Pin: - - - - ~17 16 ~14 ~1
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-- Base+$03 (EPP Address port) R/W
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-- Base+$04 (EPP Data port) R/W
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--
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--
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-- ~ indicates a hardware inversion of the bit.
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-- Parallel printer port pin assignment
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-- Parallel printer port pin assignment
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--
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--
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-- Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
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-- Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
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-- 1 nStrobe Write_n Out Control-0 Yes
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-- 1 nStrobe Write_n Out Control-0 Yes
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-- 2 Data0 Data0 In/Out Data-0 No
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-- 2 Data0 Data0 In/Out Data-0 No
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| Line 41... |
Line 46... |
-- 9 Data7 Data7 In/Out Data-7 No
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-- 9 Data7 Data7 In/Out Data-7 No
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-- 10 nAck Interrupt In Status-6 No
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-- 10 nAck Interrupt In Status-6 No
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-- 11 Busy Wait In Status-7 Yes
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-- 11 Busy Wait In Status-7 Yes
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-- 12 Paper-Out Spare In Status-5 No
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-- 12 Paper-Out Spare In Status-5 No
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-- 13 Select Spare In Status-4 No
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-- 13 Select Spare In Status-4 No
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--
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-- 14 Linefeed Data_Strobe_n Out Control-1 Yes
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-- 14 Linefeed Data_Strobe_n Out Control-1 Yes
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-- 15 nError Spare In Status-3 No
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-- 15 nError Spare In Status-3 No
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-- 16 nInitialize Reset Out Control-2 No
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-- 16 nInitialize Reset Out Control-2 No
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-- 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
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-- 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
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-- 18-25 Ground Ground - - -
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-- 18-25 Ground Ground - - -
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--
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--
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-- Address MSB LSB
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-- Copyright (C) 2008 - 2010 John Kent
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-- Bit: 7 6 5 4 3 2 1 0
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-- Base (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
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-- Base+1 (SPP Status port) Read Pin: ~11 10 12 13 15
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-- Base+2 (SPP Control port) Write Pin: ~17 16 ~14 ~1
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-- Base+3 (EPP Address port) R/W
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-- Base+4 (EPP Data port) R/W
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--
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--
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-- ~ indicates a hardware inversion of the bit.
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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--===========================================================================--
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-- --
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-- Revision History --
|
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-- --
|
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--===========================================================================--
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--
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-- Version Date Author Description
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-- 0.1 2008-09-06 John Kent Initial version generated from ioport.vhd
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-- 0.2 2010-08-09 John Kent Updated Header and added GPL
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--
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--===========================================================================
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
|
|
|
