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-- ---------------------------------------------------
 
--===========================================================================--
 
-- Video Display terminal
 
--                                                                           --
 
-- ---------------------------------------------------
 
--  vdu8.vhd - Synthesizable Colour Video Display Unit for System09          --
 
-- John Kent
 
--                                                                           --
 
-- 3th September 2004
 
--===========================================================================--
 
-- Assumes a pixel clock input of 25 MHz
 
--
 
--
 
--  File name      : vdu8.vhd
 
-- Display Format is:
 
--
 
-- 80 characters across by 25 characters down.
 
--  Purpose        : Implements a text based Colour Video Display Unit for System09
 
-- 8 horizontal pixels / character
 
--                   Supports 2KByte Text buffer and 2KByte Attribute memory
 
-- 16 vertical scan lines / character (2 scan lines/row)
 
--                   Displays 80 characters across by 25 character rows
 
 
 
--                   Characters are 8 pixels across x 16 lines down.
 
 
 
--                   Character attribute bita for foreground and backgrond colour
 
 
 
--                   1 bit for each Blue Green and Red signal
 
 
 
--                   Supports 2 x 8 chunky graphics character mode.
 
 
 
--                   Uses Generic arguments for setting the video synchronization timing.
 
 
 
--                  
 
 
--  Dependencies   : ieee.Std_Logic_1164
 
 
 
--                   ieee.std_logic_unsigned
 
 
 
--                   ieee.std_logic_arith
 
 
 
--                   ieee.numeric_std
 
 
 
--
 
 
 
--  Uses           : ram_2k (ram2k_b16.vhd)             2KByte Character & Attribute buffer
 
 
 
--                   char_rom (char_rom2k_b16.vhd)      2KByte Character Generator ROM 
 
 
--
 
 
 
--  Author         : John E. Kent
 
 
 
--
 
 
 
--  Email          : dilbert57@opencores.org      
 
 
--
 
 
 
--  Web            : http://opencores.org/project,system09
 
 
 
--
 
 
 
--  Description    : Display Timing:
 
 
 
--                       800 pixels / line
 
 
 
--                       446 lines / frame
 
 
 
--                       None interlaced
 
 
 
--                       25MHz pixel clock implies 
 
 
--                       31.25 KHz line rate
 
 
 
--                       70.067 Hz frame rate   
 
 
--                       Timing settable by generics.
 
 
 
--
 
 
 
--                   Display Size:
 
 
 
--                       80 characters across
 
 
 
--                       25 characters down.
 
 
 
--
 
 
 
--                   Character Size:
 
 
 
--                        8 horizontal pixels across
 
 
 
--                       16 vertical scan lines down (2 scan lines/row)
 
 
 
--
 
 
 
--                   Registers:
 
 
 
--                   Base + 0 ASCII character register
 
 
 
--                            Writing to this register writes an 8 bit byte 
 
 
--                            into the text buffer at the specified cursor position
 
 
 
--                            Text Mode: ASCII Character (0 to 127)
 
 
 
--                            Chunky Graphics Mode: B0 B1 (0 to 255)
 
 
 
--                                                  B2 B3
 
 
 
--                                                  B4 B5
 
 
 
--                                                  B6 B7
 
 
 
--                   Base + 1 Attibute bit (0 to 255)
 
 
 
--                            Writing to the register writes an 8 bit byte 
 
 
--                            into the attribute buffer at the specified cursor position
 
 
 
--                            B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
 
 
 
--                            B6 - 1 => Character Background Blue
 
 
 
--                            B5 - 1 => Character Background Green
 
 
 
--                            B4 - 1 => Character Background Red
 
 
 
--                            B3 - 1 => Character Background & Foreground Alternates
 
 
 
--                            B2 - 1 => Character Foreground Blue
 
 
 
--                            B1 - 1 => Character Foreground Green
 
 
 
--                            B0 - 1 => Character Foreground Red
 
 
 
--                   Base + 2 Cursor Horizontal Position (0 to 79)
 
 
 
--                   Base + 3 Cusror Vertical Position (0 to 24)
 
 
 
--                   Base + 4 Vertical Scroll Offset (0 to 24)
 
 
 
--                            Scrolls the display up by the specified number of character rows
 
 
 
--
 
 
 
--  Video Timing :
 
 
 
--
 
 
 
--  Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
 
 
 
--  /--------------------------\_____________/---------------\______________/
 
 
 
--      640 Pixels Display       16 Pixel FP    96 Pixel HS     48 Pixel BP
 
 
 
--    
 
 
--      VGA_CLK_FREQ           : integer := 25000000; -- HZ
 
 
 
--           VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
 
 
 
--           VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
 
 
 
--           VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
 
 
 
--           VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS 0.32us
 
 
 
--           VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
 
 
 
--
 
 
 
--  Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency  
 
 
--  /---------------------------\____________/---------------\______________/
 
 
 
--      400 Line Display          10 Line FP     2 Line VS      34 Line BP
 
 
 
--
 
 
 
--           VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
 
 
 
--           VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
 
 
 
--           VGA_VER_BACK_PORCH     : integer := 34; -- LINES 1.088ms
 
 
 
--           VGA_LIN_PER_CHAR       : integer := 16; -- LINES 0.512ms
 
 
 
--           VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
 
 
 
--
 
 
 
--  Copyright (C) 2003 - 2010 John Kent
 
 
 
--
 
 
 
--  This program is free software: you can redistribute it and/or modify
 
 
 
--  it under the terms of the GNU General Public License as published by
 
 
 
--  the Free Software Foundation, either version 3 of the License, or
 
 
 
--  (at your option) any later version.
 
 
 
--
 
 
 
--  This program is distributed in the hope that it will be useful,
 
 
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
 
 
--  GNU General Public License for more details.
 
 
 
--
 
 
 
--  You should have received a copy of the GNU General Public License
 
 
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 
 
--
 
 
 
--===========================================================================--
 
 
 
--                                                                           --
 
 
 
--                              Revision  History                            --
 
 
 
--                                                                           --
 
 
 
--===========================================================================--
 
--
 
--
 
-- Modified by Bert Cuzeau for compliance and code cleanliness
 
-- Version Author      Date        Changes
 
 
 
--
 
 
 
-- 0.1     John Kent   2004-09-03  Initial release
 
 
 
--
 
 
 
-- 0.2     Bert Cuzeau 2007-01-16  Modified by for compliance and code cleanliness
 
-- The effort is not over.
 
-- The effort is not over.
 
-- There are still signal initialized, which is BAD.\
 
--                                 There are still signal initialized, which is BAD.
 
 
 
--
 
 
 
-- 0.3     John Kent   2007-02-07  Added generics for VGA Timing
 
--
 
--
 
-- 7th Februaury 2007 - John Kent
 
-- 0.4     John Kent   2010-07-03  Added GPL notice. 
-- Added generics for VGA Timing
 
--                                 Updated description.
 
 
 
--                                 Rearranged Video Timing
 
--
 
--
 
 
 
 
 
Library IEEE;
 
Library IEEE;
 
  use IEEE.std_logic_1164.all;
 
  use IEEE.std_logic_1164.all;
 
  use IEEE.numeric_std.all;
 
  use IEEE.numeric_std.all;
 
Library unisim;
 
Library unisim;
 
  use unisim.vcomponents.all;
 
  use unisim.vcomponents.all;
 
 
 
 
 
Entity vdu8 is
 
Entity vdu8 is
 
  generic(
 
  generic(
 
        VDU_CLOCK_FREQUENCY    : integer := 12500000; -- HZ
 
        VGA_CLK_FREQ           : integer := 25000000; -- HZ
 
        VGA_CLOCK_FREQUENCY    : integer := 25000000; -- HZ
 
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
 
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
 
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
 
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
 
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
 
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
 
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
 
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
 
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
 
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
 
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
 
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
 
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
 
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
 
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
 
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
 
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
 
             VGA_VER_SYNC           : integer := 1;  -- LINES
 
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
 
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
 
 
 
  );
 
  );
 
  port(
 
  port(
 
    -- control register interface
 
    -- control register interface
 
    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
 
    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
 
    vdu_rst      : in  std_logic;
 
    vdu_rst      : in  std_logic;
Line 64... Line 175... 
  -- Synchronisation constants
 
  -- Synchronisation constants
 
  --
 
  --
 
  -- Displayed Characters per row
 
  -- Displayed Characters per row
 
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
 
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
 
  -- Last horizontal pixel displayed
 
  -- Last horizontal pixel displayed
 
  constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_PIXELS_PER_CHAR) - 1;
 
  constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
 
  -- Start of horizontal synch pulse
 
  -- Start of horizontal synch pulse
 
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_BACK_PORCH;
 
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
 
  -- End of Horizontal Synch pulse
 
  -- End of Horizontal Synch pulse
 
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
 
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
 
  -- Last pixel in scan line
 
  -- Last pixel in scan line
 
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_FRONT_PORCH;
 
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
 
 
 
 
 
  -- Displayed Characters per Column
 
  -- Displayed Characters per Column
 
  constant VER_DISP_CHR : integer := VGA_VER_CHARS;
 
  constant VER_DISP_CHR : integer := VGA_VER_CHARS;
 
  -- last row displayed
 
  -- last row displayed
 
  constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_LINES_PER_CHAR) - 1;
 
  constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
 
  -- start of vertical synch pulse
 
  -- start of vertical synch pulse
 
  constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_BACK_PORCH;
 
  constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
 
  -- end of vertical synch pulse
 
  -- end of vertical synch pulse
 
  constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
 
  constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
 
  -- Last scan row in the frame
 
  -- Last scan row in the frame
 
  constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_FRONT_PORCH;
 
  constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
 
 
 
 
 
  signal horiz_sync    : std_logic := '1';
 
  signal horiz_sync    : std_logic := '1';
 
  signal vert_sync     : std_logic := '1';
 
  signal vert_sync     : std_logic := '1';
 
  signal cursor_on_v   : std_logic;
 
  signal cursor_on_v   : std_logic;
 
  signal cursor_on_h   : std_logic;
 
  signal cursor_on_h   : std_logic;
Line 153... Line 264... 
      clk   : in  std_logic;
 
      clk   : in  std_logic;
 
      rst   : in  std_logic;
 
      rst   : in  std_logic;
 
      cs    : in  std_logic;
 
      cs    : in  std_logic;
 
      rw    : in  std_logic;
 
      rw    : in  std_logic;
 
      addr  : in  std_logic_vector (10 downto 0);
 
      addr  : in  std_logic_vector (10 downto 0);
 
      wdata : in std_logic_vector (7 downto 0);
 
      data_in  : in std_logic_vector (7 downto 0);
 
      rdata : out std_logic_vector (7 downto 0)
 
      data_out : out std_logic_vector (7 downto 0)
 
      );
 
      );
 
  end component;
 
  end component;
 
 
 
 
 
  component ram_2k
 
  component ram_2k
 
    port (
 
    port (
 
      clk   : in  std_logic;
 
      clk   : in  std_logic;
 
      rst   : in  std_logic;
 
      rst   : in  std_logic;
 
      cs    : in  std_logic;
 
      cs    : in  std_logic;
 
--      r_wn  : in  std_logic;
 
 
 
      rw    : in  std_logic;
 
      rw    : in  std_logic;
 
      addr  : in  std_logic_vector (10 downto 0);
 
      addr  : in  std_logic_vector (10 downto 0);
 
      wdata : in  std_logic_vector (7 downto 0);
 
      data_in  : in  std_logic_vector (7 downto 0);
 
      rdata : out std_logic_vector (7 downto 0)
 
      data_out : out std_logic_vector (7 downto 0)
 
      );
 
      );
 
  end component;
 
  end component;
 
 
 
 
 
begin
 
begin
 
 
 
 
Line 182... Line 292... 
    clk   => vga_clk,
 
    clk   => vga_clk,
 
         rst   => vdu_rst,
 
         rst   => vdu_rst,
 
         cs    => '1',
 
         cs    => '1',
 
         rw    => '1',
 
         rw    => '1',
 
    addr  => char_addr,
 
    addr  => char_addr,
 
    wdata => "00000000",
 
        data_in  => "00000000",
 
    rdata => char_data_out
 
        data_out => char_data_out
 
    );
 
    );
 
 
 
 
 
--
 
--
 
-- Character buffer RAM
 
-- Character buffer RAM
 
--
 
--
 
char_buff_ram : ram_2k port map(
 
char_buff_ram : ram_2k port map(
 
    clk   => vga_clk,
 
    clk   => vga_clk,
 
    rst   => vdu_rst,
 
    rst   => vdu_rst,
 
    cs    => vga_cs,
 
    cs    => vga_cs,
 
--    r_wn  => vga_rw,
 
 
 
    rw    => vga_rw,
 
    rw    => vga_rw,
 
    addr  => vga_addr,
 
    addr  => vga_addr,
 
    wdata => reg_character,
 
    data_in  => reg_character,
 
    rdata => vga_data_out
 
    data_out => vga_data_out
 
    );
 
    );
 
 
 
 
 
--
 
--
 
-- Attribute buffer RAM
 
-- Attribute buffer RAM
 
--
 
--
 
  attr_buff_ram : ram_2k port map(
 
  attr_buff_ram : ram_2k port map(
 
    clk   => vga_clk,
 
    clk   => vga_clk,
 
    rst   => vdu_rst,
 
    rst   => vdu_rst,
 
    cs    => vga_cs,
 
    cs    => vga_cs,
 
--    r_wn  => vga_rw,
 
 
 
    rw    => vga_rw,
 
    rw    => vga_rw,
 
    addr  => vga_addr,
 
    addr  => vga_addr,
 
    wdata => reg_colour,
 
    data_in  => reg_colour,
 
    rdata => attr_data_out
 
    data_out => attr_data_out
 
    );
 
    );
 
 
 
 
 
--
 
--
 
-- CPU Write interface
 
-- CPU Write interface
 
--
 
--

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