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-- ---------------------------------------------------
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--===========================================================================--
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-- Video Display terminal
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-- --
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-- ---------------------------------------------------
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-- vdu8_mono.vhd - Synthesizable Monochrome Video Display Unit for System09 --
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-- John Kent
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-- --
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-- 3th September 2004
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--===========================================================================--
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-- Assumes a pixel clock input of 25 MHz
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--
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--
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-- File name : vdu8.vhd
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-- Display Format is:
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--
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-- 80 characters across by 25 characters down.
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-- Purpose : Implements a text based Monochrome Video Display Unit for System09
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-- 8 horizontal pixels / character
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-- Supports 2KByte Text buffer.
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-- 16 vertical scan lines / character (2 scan lines/row)
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-- Displays 80 characters across by 25 character rows
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-- Characters are 8 pixels across x 16 lines down.
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-- Uses Generic arguments for setting the video synchronization timing.
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_arith
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-- ieee.numeric_std
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--
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-- Uses : ram_2k (ram2k_b16.vhd) 2KByte Character Buffer
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-- char_rom (char_rom2k_b16.vhd) 2KByte Character Generator
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--
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-- Author : John E. Kent
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--
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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-- Description : Display Timing:
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-- 800 pixels / line
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-- 446 lines / frame
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-- None interlaced
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-- 25MHz pixel clock implies
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-- 31.25 KHz line rate
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-- 70.067 Hz frame rate
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-- Timing settable by generics.
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--
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-- Display Size:
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-- 80 characters across
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-- 25 characters down.
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--
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-- Character Size:
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-- 8 horizontal pixels across
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-- 16 vertical scan lines down (2 scan lines/row)
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--
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-- Registers:
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-- Base + 0 ASCII character register
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-- Writing to this register writes an 8 bit byte
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-- into the text buffer at the specified cursor position
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-- Text Mode: ASCII Character (0 to 127)
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-- Chunky Graphics Mode: B0 B1 (0 to 255)
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-- B2 B3
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-- B4 B5
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-- B6 B7
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-- Base + 1 Reserved Attibute bit (0 to 255)
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-- Base + 2 Cursor Horizontal Position (0 to 79)
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-- Base + 3 Cusror Vertical Position (0 to 24)
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-- Base + 4 Vertical Scroll Offset (0 to 24)
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-- Scrolls the display up by the specified number of character rows
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-- Video Timing :
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--
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-- Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
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-- /--------------------------\_____________/---------------\______________/
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-- 640 Pixels Display 16 Pixel FP 96 Pixel HS 48 Pixel BP
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--
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-- VGA_CLK_FREQ : integer := 25000000; -- HZ
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-- VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us (0.94us)
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-- VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us (3.77us)
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-- VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us (1.89us)
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-- VGA_PIX_PER_CHAR : integer := 8; -- PIXELS 0.32us
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-- VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
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--
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-- Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency
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-- /---------------------------\____________/---------------\______________/
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-- 400 Line Display 10 Line FP 2 Line VS 34 Line BP
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--
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-- VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
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-- VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
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-- VGA_VER_BACK_PORCH : integer := 34; -- LINES 1.088ms
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-- VGA_LIN_PER_CHAR : integer := 16; -- LINES 0.512ms
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-- VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--
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--
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-- Modified by Bert Cuzeau for compliance and code cleanliness
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-- Version Author Date Changes
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--
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-- 0.1 John Kent 2004-09-03 Initial release
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--
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-- 0.2 Bert Cuzeau 2007-01-16 Modified by for compliance and code cleanliness
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-- The effort is not over.
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-- The effort is not over.
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-- There are still signal initialized, which is BAD.
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-- There are still signal initialized, which is BAD.
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--
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--
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-- 3rd February 2007 - John Kent
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-- 0.3 John Kent 2007-02-03 Changed vdu_clk to be derived externally from cpu_clk.
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-- changed vdu_clk to be derived externally from cpu_clk.
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-- Removed attibute memory for monochrome character only version.
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-- Removed attibute memory for monochrome character only version.
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-- This was done to reduce Bock RAM allocation
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--
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-- 0.4 John Kent 2007-07-01 Added generics for VGA timing specification
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--
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--
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-- 1st July 20007 - John Kent
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-- 0.5 John Kent 2010-07-03 Added GPL notice.
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-- Added generics for timing specification.
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-- Updated description
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--
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--
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Library IEEE;
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Library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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Entity vdu8_mono is
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Entity vdu8_mono is
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generic(
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generic(
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VDU_CLOCK_FREQUENCY : integer := 12500000; -- HZ
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VGA_CLK_FREQ : integer := 25000000; -- HZ
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VGA_CLOCK_FREQUENCY : integer := 25000000; -- HZ
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VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
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VGA_HOR_CHARS : integer := 80; -- CHARACTERS
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VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
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VGA_VER_CHARS : integer := 25; -- CHARACTERS
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VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
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VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
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VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
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VGA_LINES_PER_CHAR : integer := 16; -- LINES
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VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
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VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
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VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
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VGA_HOR_SYNC : integer := 96; -- PIXELS
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VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
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VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
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VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
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VGA_VER_BACK_PORCH : integer := 13; -- LINES
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VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
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VGA_VER_SYNC : integer := 1; -- LINES
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VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
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VGA_VER_FRONT_PORCH : integer := 36 -- LINES
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);
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);
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port(
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port(
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-- control register interface
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-- control register interface
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vdu_clk : in std_logic; -- 12.5/25 MHz CPU Clock
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vdu_clk : in std_logic; -- 12.5/25 MHz CPU Clock
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vdu_rst : in std_logic;
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vdu_rst : in std_logic;
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Line 69... |
Line 165... |
-- Synchronisation constants
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-- Synchronisation constants
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--
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--
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-- Displayed Characters per row
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-- Displayed Characters per row
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constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
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constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
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-- Last horizontal pixel displayed
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-- Last horizontal pixel displayed
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constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_PIXELS_PER_CHAR) - 1;
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constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
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-- Start of horizontal synch pulse
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-- Start of horizontal synch pulse
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constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_BACK_PORCH;
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constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
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-- End of Horizontal Synch pulse
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-- End of Horizontal Synch pulse
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constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
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constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
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-- Last pixel in scan line
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-- Last pixel in scan line
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constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_FRONT_PORCH;
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constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
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-- Displayed Characters per Column
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-- Displayed Characters per Column
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constant VER_DISP_CHR : integer := VGA_VER_CHARS;
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constant VER_DISP_CHR : integer := VGA_VER_CHARS;
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-- last row displayed
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-- last row displayed
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constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_LINES_PER_CHAR) - 1;
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constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
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-- start of vertical synch pulse
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-- start of vertical synch pulse
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constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_BACK_PORCH;
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constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
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-- end of vertical synch pulse
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-- end of vertical synch pulse
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constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
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constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
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-- Last scan row in the frame
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-- Last scan row in the frame
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constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_FRONT_PORCH;
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constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
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signal horiz_sync : std_logic := '1';
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signal horiz_sync : std_logic := '1';
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signal vert_sync : std_logic := '1';
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signal vert_sync : std_logic := '1';
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signal cursor_on_v : std_logic;
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signal cursor_on_v : std_logic;
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signal cursor_on_h : std_logic;
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signal cursor_on_h : std_logic;
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Line 155... |
Line 251... |
clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (10 downto 0);
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addr : in std_logic_vector (10 downto 0);
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wdata : in std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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rdata : out std_logic_vector (7 downto 0)
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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component ram_2k
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component ram_2k
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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-- r_wn : in std_logic;
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rw : in std_logic;
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rw : in std_logic;
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addr : in std_logic_vector (10 downto 0);
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addr : in std_logic_vector (10 downto 0);
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wdata : in std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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rdata : out std_logic_vector (7 downto 0)
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data_out : out std_logic_vector (7 downto 0)
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);
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);
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end component;
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end component;
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begin
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begin
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Line 184... |
Line 279... |
clk => vga_clk,
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clk => vga_clk,
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rst => vdu_rst,
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rst => vdu_rst,
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cs => '1',
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cs => '1',
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rw => '1',
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rw => '1',
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addr => char_addr,
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addr => char_addr,
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wdata => "00000000",
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data_in => "00000000",
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rdata => char_data_out
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data_out => char_data_out
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);
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);
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--
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--
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-- Character buffer RAM
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-- Character buffer RAM
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--
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--
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char_buff_ram : ram_2k port map(
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char_buff_ram : ram_2k port map(
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clk => vga_clk,
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clk => vga_clk,
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rst => vdu_rst,
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rst => vdu_rst,
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cs => vga_cs,
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cs => vga_cs,
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-- r_wn => vga_rw,
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rw => vga_rw,
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rw => vga_rw,
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addr => vga_addr,
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addr => vga_addr,
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wdata => reg_character,
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data_in => reg_character,
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rdata => vga_data_out
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data_out => vga_data_out
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);
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);
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--
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--
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-- CPU Write interface
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-- CPU Write interface
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--
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--
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