| Line 16... |
Line 16... |
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (12 downto 0);
|
addr : in std_logic_vector (12 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end flex_ram;
|
end flex_ram;
|
|
|
architecture rtl of flex_ram is
|
architecture rtl of flex_ram is
|
|
|
| Line 44... |
Line 44... |
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (10 downto 0);
|
addr : in std_logic_vector (10 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
component FLEX9_C800
|
component FLEX9_C800
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (10 downto 0);
|
addr : in std_logic_vector (10 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
component FLEX9_D000
|
component FLEX9_D000
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (10 downto 0);
|
addr : in std_logic_vector (10 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
component FLEX9_D800
|
component FLEX9_D800
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (10 downto 0);
|
addr : in std_logic_vector (10 downto 0);
|
rdata : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
wdata : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
|
|
| Line 90... |
Line 90... |
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
cs => cs0,
|
cs => cs0,
|
rw => rw,
|
rw => rw,
|
addr => addr(10 downto 0),
|
addr => addr(10 downto 0),
|
wdata => wdata,
|
data_in => data_in,
|
rdata => rdata0
|
data_out => rdata0
|
);
|
);
|
|
|
addr_c800 : FLEX9_C800 port map (
|
addr_c800 : FLEX9_C800 port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
cs => cs1,
|
cs => cs1,
|
rw => rw,
|
rw => rw,
|
addr => addr(10 downto 0),
|
addr => addr(10 downto 0),
|
wdata => wdata,
|
data_in => data_in,
|
rdata => rdata1
|
data_out => rdata1
|
);
|
);
|
addr_d000 : FLEX9_D000 port map (
|
addr_d000 : FLEX9_D000 port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
cs => cs2,
|
cs => cs2,
|
rw => rw,
|
rw => rw,
|
addr => addr(10 downto 0),
|
addr => addr(10 downto 0),
|
wdata => wdata,
|
data_in => data_in,
|
rdata => rdata2
|
data_out => rdata2
|
);
|
);
|
addr_d800 : FLEX9_D800 port map (
|
addr_d800 : FLEX9_D800 port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
cs => cs3,
|
cs => cs3,
|
rw => rw,
|
rw => rw,
|
addr => addr(10 downto 0),
|
addr => addr(10 downto 0),
|
wdata => wdata,
|
data_in => data_in,
|
rdata => rdata3
|
data_out => rdata3
|
);
|
);
|
|
|
my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
|
my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
|
begin
|
begin
|
we <= not rw;
|
we <= not rw;
|
| Line 131... |
Line 131... |
when "00" =>
|
when "00" =>
|
cs0 <= cs;
|
cs0 <= cs;
|
cs1 <= '0';
|
cs1 <= '0';
|
cs2 <= '0';
|
cs2 <= '0';
|
cs3 <= '0';
|
cs3 <= '0';
|
rdata <= rdata0;
|
data_out <= rdata0;
|
when "01" =>
|
when "01" =>
|
cs0 <= '0';
|
cs0 <= '0';
|
cs1 <= cs;
|
cs1 <= cs;
|
cs2 <= '0';
|
cs2 <= '0';
|
cs3 <= '0';
|
cs3 <= '0';
|
rdata <= rdata1;
|
data_out <= rdata1;
|
when "10" =>
|
when "10" =>
|
cs0 <= '0';
|
cs0 <= '0';
|
cs1 <= '0';
|
cs1 <= '0';
|
cs2 <= cs;
|
cs2 <= cs;
|
cs3 <= '0';
|
cs3 <= '0';
|
rdata <= rdata2;
|
data_out <= rdata2;
|
when "11" =>
|
when "11" =>
|
cs0 <= '0';
|
cs0 <= '0';
|
cs1 <= '0';
|
cs1 <= '0';
|
cs2 <= '0';
|
cs2 <= '0';
|
cs3 <= cs;
|
cs3 <= cs;
|
rdata <= rdata3;
|
data_out <= rdata3;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
