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https://opencores.org/ocsvn/System11/System11/trunk
[/] [System11/] [trunk/] [rtl/] [vhdl/] [System11.npl] - Diff between revs 2 and 4
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// Created by ISE ver 1.0
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// Created by Project Navigator ver 1.0
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PROJECT System11
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PROJECT System11
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DESIGN system11 Normal
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DESIGN system11
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DEVKIT xc2s300e-6pq208
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DEVFAM spartan2e
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DEVFAM spartan2e
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FLOW XST VHDL
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DEVFAMTIME 315558000
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STIMULUS testbench1.vhd Normal
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DEVICE xc2s300e
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STIMULUS testbench2.vhd Normal
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DEVICETIME 315558000
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STIMULUS testbench3.vhd Normal
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DEVPKG pq208
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MODULE ioport.vhd
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DEVPKGTIME 315558000
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MODSTYLE ioport Normal
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DEVSPEED -6
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MODULE cpu11.vhd
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DEVSPEEDTIME 315558000
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MODSTYLE cpu11 Normal
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DEVTOPLEVELMODULETYPE HDL
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MODULE rxunit.vhd
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TOPLEVELMODULETYPETIME 0
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MODSTYLE rxunit Normal
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DEVSYNTHESISTOOL XST (VHDL/Verilog)
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MODULE swtbug11.vhd
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SYNTHESISTOOLTIME 0
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MODSTYLE boot_rom Normal
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DEVSIMULATOR Modelsim
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MODULE txunit.vhd
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SIMULATORTIME 0
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MODSTYLE txunit Normal
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DEVGENERATEDSIMULATIONMODEL VHDL
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MODULE datram.vhd
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GENERATEDSIMULATIONMODELTIME 0
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MODSTYLE dat_ram Normal
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STIMULUS testbench1.vhd
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MODULE timer.vhd
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STIMULUS testbench2.vhd
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MODSTYLE timer Normal
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STIMULUS testbench3.vhd
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MODULE System11.vhd
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SOURCE ioport.vhd
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MODSTYLE system11 Normal
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SOURCE cpu11.vhd
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MODULE clkunit.vhd
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SOURCE swtbug11.vhd
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MODSTYLE clkunit Normal
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SOURCE datram.vhd
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MODULE miniUART.vhd
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SOURCE timer.vhd
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MODSTYLE miniuart Normal
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SOURCE System11.vhd
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SOURCE rxunit3.vhd
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SOURCE txunit3.vhd
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SOURCE miniUART3.vhd
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STIMULUS testbench4.vhd
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SOURCE tb_ram.vhd
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STIMULUS testbench5.vhd
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DEPASSOC system11 system11.ucf
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[Normal]
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[Normal]
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p_impactConfigMode=xstvhd, SPARTAN2E, VHDL.t_impactProgrammingTool, 1062755889, Slave Serial
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p_impactConfigMode=xstvhd, spartan2e, Implementation.t_impactProgrammingTool, 1062755889, Slave Serial
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p_ModelSimSimRunTime_tbw=xstvhd, spartan2e, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
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[STATUS-ALL]
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system11.bitgenGroup=OK,1084885833
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[STRATEGY-LIST]
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[STRATEGY-LIST]
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Normal=True, 1062754578
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Normal=True
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Normal=True
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Normal=True
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