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https://opencores.org/ocsvn/System11/System11/trunk
[/] [System11/] [trunk/] [rtl/] [vhdl/] [datram.vhd] - Diff between revs 2 and 4
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Rev 4 |
Line 89... |
Line 89... |
--
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--
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---------------------------------
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---------------------------------
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dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
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dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
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begin
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begin
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if clk'event and clk = '0' then
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if rst = '1' then
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if rst = '1' then
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dat_reg0 <= "00000000";
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dat_reg0 <= "00000000";
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dat_reg1 <= "00000001";
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dat_reg1 <= "00000001";
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dat_reg2 <= "00000010";
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dat_reg2 <= "00000010";
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dat_reg3 <= "00000011";
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dat_reg3 <= "00000011";
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Line 107... |
Line 106... |
dat_reg11 <= "00001011";
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dat_reg11 <= "00001011";
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dat_reg12 <= "00001100";
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dat_reg12 <= "00001100";
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dat_reg13 <= "00001101";
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dat_reg13 <= "00001101";
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dat_reg14 <= "00001110";
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dat_reg14 <= "00001110";
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dat_reg15 <= "00001111";
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dat_reg15 <= "00001111";
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else
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elsif clk'event and clk = '0' then
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if cs = '1' and rw = '0' then
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if cs = '1' and rw = '0' then
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case addr_lo is
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case addr_lo is
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when "0000" =>
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when "0000" =>
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dat_reg0 <= data_in;
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dat_reg0 <= data_in;
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when "0001" =>
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when "0001" =>
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Line 147... |
Line 146... |
when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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dat_read : process( addr_hi,
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dat_read : process( addr_hi,
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dat_reg0, dat_reg1, dat_reg2, dat_reg3,
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dat_reg0, dat_reg1, dat_reg2, dat_reg3,
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dat_reg4, dat_reg5, dat_reg6, dat_reg7,
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dat_reg4, dat_reg5, dat_reg6, dat_reg7,
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