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[/] [System11/] [trunk/] [rtl/] [vhdl/] [datram.vhd] - Diff between revs 2 and 4

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Rev 2 Rev 4
Line 89... Line 89...
--
--
---------------------------------
---------------------------------
 
 
dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
begin
begin
  if clk'event and clk = '0' then
 
    if rst = '1' then
    if rst = '1' then
      dat_reg0 <= "00000000";
      dat_reg0 <= "00000000";
      dat_reg1 <= "00000001";
      dat_reg1 <= "00000001";
      dat_reg2 <= "00000010";
      dat_reg2 <= "00000010";
      dat_reg3 <= "00000011";
      dat_reg3 <= "00000011";
Line 107... Line 106...
      dat_reg11 <= "00001011";
      dat_reg11 <= "00001011";
      dat_reg12 <= "00001100";
      dat_reg12 <= "00001100";
      dat_reg13 <= "00001101";
      dat_reg13 <= "00001101";
      dat_reg14 <= "00001110";
      dat_reg14 <= "00001110";
      dat_reg15 <= "00001111";
      dat_reg15 <= "00001111";
    else
    elsif clk'event and clk = '0' then
           if cs = '1' and rw = '0' then
           if cs = '1' and rw = '0' then
        case addr_lo is
        case addr_lo is
             when "0000" =>
             when "0000" =>
                    dat_reg0 <= data_in;
                    dat_reg0 <= data_in;
             when "0001" =>
             when "0001" =>
Line 147... Line 146...
        when others =>
        when others =>
                    null;
                    null;
                  end case;
                  end case;
           end if;
           end if;
         end if;
         end if;
  end if;
 
end process;
end process;
 
 
dat_read : process(  addr_hi,
dat_read : process(  addr_hi,
                     dat_reg0, dat_reg1, dat_reg2, dat_reg3,
                     dat_reg0, dat_reg1, dat_reg2, dat_reg3,
                     dat_reg4, dat_reg5, dat_reg6, dat_reg7,
                     dat_reg4, dat_reg5, dat_reg6, dat_reg7,

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