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Line 12... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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entity my_testbench is
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entity my_testbench1 is
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end my_testbench;
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end my_testbench1;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for memio Controller Unit
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-- Architecture for Testbench 1
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture behavior of my_testbench is
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architecture behavior of my_testbench1 is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal uart_irq : Std_Logic;
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signal uart_irq : Std_Logic;
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signal timer_irq : std_logic;
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signal timer_irq : std_logic;
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Line 84... |
vma: out std_logic;
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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address: out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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irq: in std_logic;
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irq: in std_logic;
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xirq: in std_logic;
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xirq: in std_logic
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test_alu: out std_logic_vector(15 downto 0);
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test_cc: out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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begin
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begin
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Line 99... |
vma => cpu_vma,
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vma => cpu_vma,
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address => cpu_addr(15 downto 0),
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address => cpu_addr(15 downto 0),
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data_in => cpu_data_in,
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data_in => cpu_data_in,
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data_out => cpu_data_out,
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data_out => cpu_data_out,
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irq => uart_irq,
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irq => uart_irq,
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xirq => timer_irq,
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xirq => timer_irq
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test_alu => cpu_alu,
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test_cc => cpu_cc
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);
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);
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-- *** Test Bench - User Defined Section ***
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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tb : PROCESS
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variable count : integer;
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variable count : integer;
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